diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll index fd5e1389176..42d7bc0e777 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll @@ -3,7 +3,7 @@ ; GCN-LABEL: {{^}}sample: ; GCN: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -12,7 +12,7 @@ main_body: ; GCN-LABEL: {{^}}sample_cl: ; GCN: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -21,7 +21,7 @@ main_body: ; GCN-LABEL: {{^}}sample_d: ; GCN: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_d(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_d(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -30,7 +30,7 @@ main_body: ; GCN-LABEL: {{^}}sample_d_cl: ; GCN: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_d_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_d_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -39,7 +39,7 @@ main_body: ; GCN-LABEL: {{^}}sample_l: ; GCN: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_l(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_l(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -48,7 +48,7 @@ main_body: ; GCN-LABEL: {{^}}sample_b: ; GCN: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_b(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_b(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -57,7 +57,7 @@ main_body: ; GCN-LABEL: {{^}}sample_b_cl: ; GCN: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_b_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_b_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -66,7 +66,7 @@ main_body: ; GCN-LABEL: {{^}}sample_lz: ; GCN: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_lz(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_lz(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -75,7 +75,7 @@ main_body: ; GCN-LABEL: {{^}}sample_cd: ; GCN: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_cd(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_cd(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -84,7 +84,7 @@ main_body: ; GCN-LABEL: {{^}}sample_cd_cl: ; GCN: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_cd_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_cd_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -93,7 +93,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c: ; GCN: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -102,7 +102,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_cl: ; GCN: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -111,7 +111,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_d: ; GCN: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_d(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_d(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -120,7 +120,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_d_cl: ; GCN: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_d_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_d_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -129,7 +129,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_l: ; GCN: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_l(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_l(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -138,7 +138,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_b: ; GCN: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_b(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_b(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -147,7 +147,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_b_cl: ; GCN: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_b_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_b_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -156,7 +156,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_lz: ; GCN: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_lz(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_lz(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -165,7 +165,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_cd: ; GCN: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_cd(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_cd(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -174,7 +174,7 @@ main_body: ; GCN-LABEL: {{^}}sample_c_cd_cl: ; GCN: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf -define void @sample_c_cd_cl(<4 x float> addrspace(1)* %out) { +define amdgpu_kernel void @sample_c_cd_cl(<4 x float> addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0) store <4 x float> %r, <4 x float> addrspace(1)* %out @@ -184,7 +184,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -195,7 +195,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -206,7 +206,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_d_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_d_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_d_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -217,7 +217,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_d_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_d_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_d_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -228,7 +228,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_l_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_l_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_l_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -239,7 +239,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_b_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_b_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_b_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -250,7 +250,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_b_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_b_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_b_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -261,7 +261,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_lz_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_lz_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_lz_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -272,7 +272,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_cd_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_cd_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_cd_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -283,7 +283,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_cd_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_cd_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_cd_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -294,7 +294,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -305,7 +305,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -316,7 +316,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_d_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_d_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_d_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -327,7 +327,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_d_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_d_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_d_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -338,7 +338,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_l_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_l_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_l_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -349,7 +349,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_b_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_b_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_b_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -360,7 +360,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_b_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_b_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_b_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -371,7 +371,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_lz_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_lz_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_lz_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -382,7 +382,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_cd_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_cd_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_cd_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 @@ -393,7 +393,7 @@ main_body: ; GCN-LABEL: {{^}}adjust_writemask_sample_c_cd_cl_o_none_enabled: ; GCN-NOT: image ; GCN-NOT: store -define void @adjust_writemask_sample_c_cd_cl_o_none_enabled(float addrspace(1)* %out) { +define amdgpu_kernel void @adjust_writemask_sample_c_cd_cl_o_none_enabled(float addrspace(1)* %out) { main_body: %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false) %elt0 = extractelement <4 x float> %r, i32 0 |
