diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll index c81a0a48726..a6a402b93bf 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll @@ -274,9 +274,9 @@ define amdgpu_kernel void @v_fcmp_f16(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_oeq: ; VI: v_cmp_eq_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_oeq(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1) store i64 %result, i64 addrspace(1)* %out @@ -286,9 +286,9 @@ define amdgpu_kernel void @v_fcmp_f16_oeq(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_one: ; VI: v_cmp_neq_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_one(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6) store i64 %result, i64 addrspace(1)* %out @@ -298,9 +298,9 @@ define amdgpu_kernel void @v_fcmp_f16_one(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_ogt: ; VI: v_cmp_gt_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_gt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_lt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_ogt(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2) store i64 %result, i64 addrspace(1)* %out @@ -310,9 +310,9 @@ define amdgpu_kernel void @v_fcmp_f16_ogt(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_oge: ; VI: v_cmp_ge_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_ge_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_le_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_oge(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3) store i64 %result, i64 addrspace(1)* %out @@ -322,9 +322,9 @@ define amdgpu_kernel void @v_fcmp_f16_oge(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_olt: ; VI: v_cmp_lt_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_lt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_gt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_olt(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4) store i64 %result, i64 addrspace(1)* %out @@ -334,9 +334,9 @@ define amdgpu_kernel void @v_fcmp_f16_olt(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_ole: ; VI: v_cmp_le_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_le_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_ge_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_ole(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5) store i64 %result, i64 addrspace(1)* %out @@ -346,9 +346,9 @@ define amdgpu_kernel void @v_fcmp_f16_ole(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_ueq: ; VI: v_cmp_nlg_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_nlg_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_nlg_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_ueq(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9) store i64 %result, i64 addrspace(1)* %out @@ -358,9 +358,9 @@ define amdgpu_kernel void @v_fcmp_f16_ueq(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_une: ; VI: v_cmp_neq_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_une(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14) store i64 %result, i64 addrspace(1)* %out @@ -370,9 +370,9 @@ define amdgpu_kernel void @v_fcmp_f16_une(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_ugt: ; VI: v_cmp_nle_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_nle_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_nge_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_ugt(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10) store i64 %result, i64 addrspace(1)* %out @@ -382,9 +382,9 @@ define amdgpu_kernel void @v_fcmp_f16_ugt(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_uge: ; VI: v_cmp_nlt_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_nlt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_ngt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_uge(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11) store i64 %result, i64 addrspace(1)* %out @@ -394,9 +394,9 @@ define amdgpu_kernel void @v_fcmp_f16_uge(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_ult: ; VI: v_cmp_nge_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_nge_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_nle_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_ult(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12) store i64 %result, i64 addrspace(1)* %out @@ -406,9 +406,9 @@ define amdgpu_kernel void @v_fcmp_f16_ult(i64 addrspace(1)* %out, half %src) { ; GCN-LABEL: {{^}}v_fcmp_f16_ule: ; VI: v_cmp_ngt_f16_e64 -; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x42c80000 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}} -; SI: v_cmp_ngt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] +; SI: v_cmp_nlt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[CVT]] define amdgpu_kernel void @v_fcmp_f16_ule(i64 addrspace(1)* %out, half %src) { %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13) store i64 %result, i64 addrspace(1)* %out |
