diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll index 15daa7152f2..a7a8fa7f2cc 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll @@ -49,8 +49,8 @@ define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 { ; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}} ; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16 ; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}} -; NOLOOP-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]] -; NOLOOP: ds_gws_init v0 gds{{$}} +; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]] +; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}} define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 { call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset) ret void @@ -61,8 +61,8 @@ define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 { ; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}} ; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16 ; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}} -; NOLOOP-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]] -; NOLOOP: ds_gws_init v0 offset:1 gds{{$}} +; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]] +; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}} define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 { %offset = add i32 %offset.base, 1 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset) @@ -102,13 +102,13 @@ define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 { ; Check if m0 initialization is shared. ; GCN-LABEL: {{^}}gws_init_save_m0_init_constant_offset: ; NOLOOP: s_mov_b32 m0, 0 -; NOLOOP: ds_gws_init v0 offset:10 gds +; NOLOOP: ds_gws_init v{{[0-9]+}} offset:10 gds ; LOOP: s_mov_b32 m0, -1 ; LOOP: ds_write_b32 ; LOOP: s_mov_b32 m0, 0 ; LOOP: s_setreg_imm32_b32 -; LOOP: ds_gws_init v0 offset:10 gds +; LOOP: ds_gws_init v{{[0-9]+}} offset:10 gds ; LOOP: s_cbranch_scc1 ; LOOP: s_mov_b32 m0, -1 |
