1 files changed, 7 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll b/llvm/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll
index 55eb00949db..7cdd9559994 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll
@@ -3,7 +3,7 @@
 
 ; CHECK-LABEL: {{^}}v1:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd
-define void @v1(i32 %a1) #0 {
+define amdgpu_ps void @v1(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -16,7 +16,7 @@ entry:
 
 ; CHECK-LABEL: {{^}}v2:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb
-define void @v2(i32 %a1) #0 {
+define amdgpu_ps void @v2(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -29,7 +29,7 @@ entry:
 
 ; CHECK-LABEL: {{^}}v3:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe
-define void @v3(i32 %a1) #0 {
+define amdgpu_ps void @v3(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -42,7 +42,7 @@ entry:
 
 ; CHECK-LABEL: {{^}}v4:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7
-define void @v4(i32 %a1) #0 {
+define amdgpu_ps void @v4(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -55,7 +55,7 @@ entry:
 
 ; CHECK-LABEL: {{^}}v5:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa
-define void @v5(i32 %a1) #0 {
+define amdgpu_ps void @v5(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -67,7 +67,7 @@ entry:
 
 ; CHECK-LABEL: {{^}}v6:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6
-define void @v6(i32 %a1) #0 {
+define amdgpu_ps void @v6(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -79,7 +79,7 @@ entry:
 
 ; CHECK-LABEL: {{^}}v7:
 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9
-define void @v7(i32 %a1) #0 {
+define amdgpu_ps void @v7(i32 %a1) {
 entry:
   %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
   %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
@@ -92,5 +92,3 @@ entry:
 declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone
 
 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { "ShaderType"="0" }