diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/inline-asm.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-asm.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll index db1a0c67436..85eb163383e 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll @@ -4,7 +4,7 @@ ; CHECK-LABEL: {{^}}inline_asm: ; CHECK: s_endpgm ; CHECK: s_endpgm -define void @inline_asm(i32 addrspace(1)* %out) { +define amdgpu_kernel void @inline_asm(i32 addrspace(1)* %out) { entry: store i32 5, i32 addrspace(1)* %out call void asm sideeffect "s_endpgm", ""() @@ -25,7 +25,7 @@ entry: ; Make sure inline assembly is treted as divergent. ; CHECK: s_mov_b32 s{{[0-9]+}}, 0 ; CHECK: s_and_saveexec_b64 -define void @branch_on_asm(i32 addrspace(1)* %out) { +define amdgpu_kernel void @branch_on_asm(i32 addrspace(1)* %out) { %zero = call i32 asm "s_mov_b32 $0, 0", "=s"() %cmp = icmp eq i32 %zero, 0 br i1 %cmp, label %if, label %endif @@ -44,7 +44,7 @@ endif: ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]] ; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} -define void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { +define amdgpu_kernel void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { %sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in) store i64 %sgpr, i64 addrspace(1)* %out ret void @@ -52,7 +52,7 @@ define void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { ; CHECK-LABEL: {{^}}code_size_inline_asm: ; CHECK: codeLenInByte = 12 -define void @code_size_inline_asm(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm(i32 addrspace(1)* %out) { entry: call void asm sideeffect "v_nop_e64", ""() ret void @@ -61,7 +61,7 @@ entry: ; All inlineasm instructions are assumed to be the maximum size ; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst: ; CHECK: codeLenInByte = 12 -define void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) { entry: call void asm sideeffect "v_nop_e32", ""() ret void @@ -69,7 +69,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst: ; CHECK: codeLenInByte = 20 -define void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) { entry: call void asm sideeffect " v_nop_e64 @@ -80,7 +80,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline: ; CHECK: codeLenInByte = 20 -define void @code_size_inline_asm_2_inst_extra_newline(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_2_inst_extra_newline(i32 addrspace(1)* %out) { entry: call void asm sideeffect " v_nop_e64 @@ -92,7 +92,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst: ; CHECK: codeLenInByte = 4 -define void @code_size_inline_asm_0_inst(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_0_inst(i32 addrspace(1)* %out) { entry: call void asm sideeffect "", ""() ret void @@ -100,7 +100,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment: ; CHECK: codeLenInByte = 4 -define void @code_size_inline_asm_1_comment(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_1_comment(i32 addrspace(1)* %out) { entry: call void asm sideeffect "; comment", ""() ret void @@ -108,7 +108,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment: ; CHECK: codeLenInByte = 4 -define void @code_size_inline_asm_newline_1_comment(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_newline_1_comment(i32 addrspace(1)* %out) { entry: call void asm sideeffect " ; comment", ""() @@ -117,7 +117,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline: ; CHECK: codeLenInByte = 4 -define void @code_size_inline_asm_1_comment_newline(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_1_comment_newline(i32 addrspace(1)* %out) { entry: call void asm sideeffect "; comment ", ""() @@ -126,7 +126,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line: ; CHECK: codeLenInByte = 4 -define void @code_size_inline_asm_2_comments_line(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_2_comments_line(i32 addrspace(1)* %out) { entry: call void asm sideeffect "; first comment ; second comment", ""() ret void @@ -134,7 +134,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace: ; CHECK: codeLenInByte = 4 -define void @code_size_inline_asm_2_comments_line_nospace(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_2_comments_line_nospace(i32 addrspace(1)* %out) { entry: call void asm sideeffect "; first comment;second comment", ""() ret void @@ -142,7 +142,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0: ; CHECK: codeLenInByte = 20 -define void @code_size_inline_asm_mixed_comments0(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_mixed_comments0(i32 addrspace(1)* %out) { entry: call void asm sideeffect "; comment v_nop_e64 ; inline comment @@ -157,7 +157,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1: ; CHECK: codeLenInByte = 20 -define void @code_size_inline_asm_mixed_comments1(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_mixed_comments1(i32 addrspace(1)* %out) { entry: call void asm sideeffect "v_nop_e64 ; inline comment ; separate comment @@ -171,7 +171,7 @@ entry: ; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands: ; CHECK: codeLenInByte = 20 -define void @code_size_inline_asm_mixed_comments_operands(i32 addrspace(1)* %out) { +define amdgpu_kernel void @code_size_inline_asm_mixed_comments_operands(i32 addrspace(1)* %out) { entry: call void asm sideeffect "; comment v_add_i32_e32 v0, vcc, v1, v2 ; inline comment |
