diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir b/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir new file mode 100644 index 00000000000..348559fbd0d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir @@ -0,0 +1,50 @@ +# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s + + +# CHECK-LABEL: name: foo +# CHECK: BUFFER_STORE_DWORD_OFFSET +--- | + + define amdgpu_kernel void @foo() #0 { + ret void + } + + attributes #0 = { "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" } +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '$vgpr0' } + - { reg: '$sgpr4_sgpr5' } + - { reg: '$sgpr6_sgpr7' } + - { reg: '$sgpr8' } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, type: spill-slot, size: 4, alignment: 4 } +machineFunctionInfo: + explicitKernArgSize: 660 + maxKernArgAlign: 4 + isEntryFunction: true + waveLimiter: true + scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' + scratchWaveOffsetReg: '$sgpr101' + frameOffsetReg: '$sgpr101' + stackPtrOffsetReg: '$sgpr32' + argumentInfo: + privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } + dispatchPtr: { reg: '$sgpr4_sgpr5' } + kernargSegmentPtr: { reg: '$sgpr6_sgpr7' } + workGroupIDX: { reg: '$sgpr8' } + privateSegmentWaveByteOffset: { reg: '$sgpr9' } +body: | + bb.0: + successors: %bb.1 + liveins: $sgpr8, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7 + + bb.1: + liveins: $sgpr4, $sgpr5, $sgpr9, $sgpr22, $vgpr0, $sgpr6_sgpr7 + + renamable $vgpr2 = IMPLICIT_DEF + SI_SPILL_V32_SAVE killed $vgpr2, %stack.0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5) |
