diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/fceil.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fceil.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/fceil.ll b/llvm/test/CodeGen/AMDGPU/fceil.ll index efdda78f852..0b913fda858 100644 --- a/llvm/test/CodeGen/AMDGPU/fceil.ll +++ b/llvm/test/CodeGen/AMDGPU/fceil.ll @@ -13,7 +13,7 @@ declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone ; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: CEIL {{\*? *}}[[RESULT]] -define void @fceil_f32(float addrspace(1)* %out, float %x) { +define amdgpu_kernel void @fceil_f32(float addrspace(1)* %out, float %x) { %y = call float @llvm.ceil.f32(float %x) nounwind readnone store float %y, float addrspace(1)* %out ret void @@ -25,7 +25,7 @@ define void @fceil_f32(float addrspace(1)* %out, float %x) { ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] -define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { +define amdgpu_kernel void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { %y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone store <2 x float> %y, <2 x float> addrspace(1)* %out ret void @@ -41,7 +41,7 @@ define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { ; EG-DAG: CEIL {{\*? *}}[[RESULT1]] ; EG-DAG: CEIL {{\*? *}}[[RESULT2]] ; EG-DAG: CEIL {{\*? *}}[[RESULT2]] -define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { +define amdgpu_kernel void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { %y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone store <3 x float> %y, <3 x float> addrspace(1)* %out ret void @@ -57,7 +57,7 @@ define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] -define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { +define amdgpu_kernel void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { %y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone store <4 x float> %y, <4 x float> addrspace(1)* %out ret void @@ -82,7 +82,7 @@ define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { ; EG-DAG: CEIL {{\*? *}}[[RESULT2]] ; EG-DAG: CEIL {{\*? *}}[[RESULT2]] ; EG-DAG: CEIL {{\*? *}}[[RESULT2]] -define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { +define amdgpu_kernel void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { %y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone store <8 x float> %y, <8 x float> addrspace(1)* %out ret void @@ -125,7 +125,7 @@ define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { ; EG-DAG: CEIL {{\*? *}}[[RESULT4]] ; EG-DAG: CEIL {{\*? *}}[[RESULT4]] ; EG-DAG: CEIL {{\*? *}}[[RESULT4]] -define void @fceil_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) { +define amdgpu_kernel void @fceil_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) { %y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone store <16 x float> %y, <16 x float> addrspace(1)* %out ret void |
