diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/early-if-convert.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/early-if-convert.ll | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/early-if-convert.ll b/llvm/test/CodeGen/AMDGPU/early-if-convert.ll index 5ae1db8c686..9439130deb9 100644 --- a/llvm/test/CodeGen/AMDGPU/early-if-convert.ll +++ b/llvm/test/CodeGen/AMDGPU/early-if-convert.ll @@ -9,7 +9,7 @@ ; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], [[VAL]], [[VAL]] ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], [[ADD]], [[VAL]], vcc ; GCN: buffer_store_dword [[RESULT]] -define void @test_vccnz_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %v = load float, float addrspace(1)* %in %cc = fcmp oeq float %v, 1.000000e+00 @@ -32,7 +32,7 @@ endif: ; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[VAL]], [[VAL]] ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], [[ADD]], [[MUL]], vcc ; GCN: buffer_store_dword [[RESULT]] -define void @test_vccnz_ifcvt_diamond(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_diamond(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %v = load float, float addrspace(1)* %in %cc = fcmp oeq float %v, 1.000000e+00 @@ -58,7 +58,7 @@ endif: ; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc ; GCN: s_mov_b64 vcc, [[CMP]] ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc -define void @test_vccnz_ifcvt_triangle_vcc_clobber(i32 addrspace(1)* %out, i32 addrspace(1)* %in, float %k) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle_vcc_clobber(i32 addrspace(1)* %out, i32 addrspace(1)* %in, float %k) #0 { entry: %v = load i32, i32 addrspace(1)* %in %cc = fcmp oeq float %k, 1.000000e+00 @@ -87,7 +87,7 @@ endif: ; GCN: v_mul_f32 ; GCN: v_mul_f32 ; GCN: v_cndmask_b32_e32 -define void @test_vccnz_ifcvt_triangle_max_cheap(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle_max_cheap(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %v = load float, float addrspace(1)* %in %cc = fcmp oeq float %v, 1.000000e+00 @@ -128,7 +128,7 @@ endif: ; GCN: [[ENDIF]]: ; GCN: buffer_store_dword -define void @test_vccnz_ifcvt_triangle_min_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle_min_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %v = load float, float addrspace(1)* %in %cc = fcmp oeq float %v, 1.000000e+00 @@ -162,7 +162,7 @@ endif: ; GCN: [[ENDIF]]: ; GCN: buffer_store_dword -define void @test_vccnz_ifcvt_triangle_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %v = load float, float addrspace(1)* %in %cc = fcmp oeq float %v, 1.000000e+00 @@ -187,7 +187,7 @@ endif: ; GCN: [[ENDIF]]: ; GCN: buffer_store_dword -define void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(2)* %in, float %cnd) #0 { +define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(2)* %in, float %cnd) #0 { entry: %v = load i32, i32 addrspace(2)* %in %cc = fcmp oeq float %cnd, 1.000000e+00 @@ -206,7 +206,7 @@ endif: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_constant_load: ; GCN: v_cndmask_b32 -define void @test_vccnz_ifcvt_triangle_constant_load(float addrspace(1)* %out, float addrspace(2)* %in) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle_constant_load(float addrspace(1)* %out, float addrspace(2)* %in) #0 { entry: %v = load float, float addrspace(2)* %in %cc = fcmp oeq float %v, 1.000000e+00 @@ -227,7 +227,7 @@ endif: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_argload: ; GCN: v_cndmask_b32 -define void @test_vccnz_ifcvt_triangle_argload(float addrspace(1)* %out, float %v) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle_argload(float addrspace(1)* %out, float %v) #0 { entry: %cc = fcmp oeq float %v, 1.000000e+00 br i1 %cc, label %if, label %endif @@ -248,7 +248,7 @@ endif: ; GCN: s_add_i32 [[ADD:s[0-9]+]], [[VAL]], [[VAL]] ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN-NEXT: s_cselect_b32 [[SELECT:s[0-9]+]], [[ADD]], [[VAL]] -define void @test_scc1_sgpr_ifcvt_triangle(i32 addrspace(2)* %in, i32 %cond) #0 { +define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle(i32 addrspace(2)* %in, i32 %cond) #0 { entry: %v = load i32, i32 addrspace(2)* %in %cc = icmp eq i32 %cond, 1 @@ -274,7 +274,7 @@ endif: ; GCN: [[ENDIF]]: ; GCN: buffer_store_dword -define void @test_scc1_vgpr_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in, i32 %cond) #0 { +define amdgpu_kernel void @test_scc1_vgpr_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in, i32 %cond) #0 { entry: %v = load float, float addrspace(1)* %in %cc = icmp eq i32 %cond, 1 @@ -295,7 +295,7 @@ endif: ; GCN: s_addc_u32 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} -define void @test_scc1_sgpr_ifcvt_triangle64(i64 addrspace(2)* %in, i32 %cond) #0 { +define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle64(i64 addrspace(2)* %in, i32 %cond) #0 { entry: %v = load i64, i64 addrspace(2)* %in %cc = icmp eq i32 %cond, 1 @@ -320,7 +320,7 @@ endif: ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} -define void @test_scc1_sgpr_ifcvt_triangle96(<3 x i32> addrspace(2)* %in, i32 %cond) #0 { +define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle96(<3 x i32> addrspace(2)* %in, i32 %cond) #0 { entry: %v = load <3 x i32>, <3 x i32> addrspace(2)* %in %cc = icmp eq i32 %cond, 1 @@ -345,7 +345,7 @@ endif: ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} -define void @test_scc1_sgpr_ifcvt_triangle128(<4 x i32> addrspace(2)* %in, i32 %cond) #0 { +define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle128(<4 x i32> addrspace(2)* %in, i32 %cond) #0 { entry: %v = load <4 x i32>, <4 x i32> addrspace(2)* %in %cc = icmp eq i32 %cond, 1 @@ -364,7 +364,7 @@ endif: ; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc_constant_select: ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; GCN: s_cselect_b32 s{{[0-9]+}}, 1, 0{{$}} -define void @uniform_if_swap_br_targets_scc_constant_select(i32 %cond, i32 addrspace(1)* %out) { +define amdgpu_kernel void @uniform_if_swap_br_targets_scc_constant_select(i32 %cond, i32 addrspace(1)* %out) { entry: %cmp0 = icmp eq i32 %cond, 0 br i1 %cmp0, label %else, label %if @@ -385,7 +385,7 @@ done: ; GCN: {{^}}; BB#0: ; GCN-NEXT: s_load_dwordx2 ; GCN-NEXT: s_cselect_b32 s{{[0-9]+}}, 1, 0 -define void @ifcvt_undef_scc(i32 %cond, i32 addrspace(1)* %out) { +define amdgpu_kernel void @ifcvt_undef_scc(i32 %cond, i32 addrspace(1)* %out) { entry: br i1 undef, label %else, label %if @@ -410,7 +410,7 @@ done: ; GCN: [[ENDIF]]: ; GCN: buffer_store_dword -define void @test_vccnz_ifcvt_triangle256(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in, float %cnd) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle256(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in, float %cnd) #0 { entry: %v = load <8 x i32>, <8 x i32> addrspace(1)* %in %cc = fcmp oeq float %cnd, 1.000000e+00 @@ -435,7 +435,7 @@ endif: ; GCN: [[ENDIF]]: ; GCN: buffer_store_dword -define void @test_vccnz_ifcvt_triangle512(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in, float %cnd) #0 { +define amdgpu_kernel void @test_vccnz_ifcvt_triangle512(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in, float %cnd) #0 { entry: %v = load <16 x i32>, <16 x i32> addrspace(1)* %in %cc = fcmp oeq float %cnd, 1.000000e+00 |
