1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
index 05d8dc0b9a0..1314311c9cd 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
@@ -21,6 +21,21 @@ entry:
   ret void
 }
 
+; GFX9-LABEL: {{^}}write_ds_sub0_offset0_global_clamp_bit:
+; GFX9: v_sub_u32
+; GFX9: s_endpgm
+define amdgpu_kernel void @write_ds_sub0_offset0_global_clamp_bit(float %dummy.val) #0 {
+entry:
+  %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
+  %sub1 = sub i32 0, %x.i
+  %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
+  store i32 123, i32 addrspace(3)* %arrayidx
+  %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
+  store volatile float %fmas, float addrspace(1)* null
+  ret void
+}
+
 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
@@ -112,6 +127,21 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {
   ret void
 }
 
+; GFX9-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:
+; GFX9: v_sub_u32
+; GFX9: s_endpgm
+define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit(float %dummy.val) #1 {
+  %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
+  %neg = sub i32 0, %x.i
+  %shl = shl i32 %neg, 2
+  %add = add i32 1019, %shl
+  %ptr = inttoptr i32 %add to i64 addrspace(3)*
+  store i64 123, i64 addrspace(3)* %ptr, align 4
+  %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
+  store volatile float %fmas, float addrspace(1)* null
+  ret void
+}
+
 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
@@ -127,6 +157,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #
   ret void
 }
 
+declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1)
+
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }
 attributes #2 = { nounwind convergent }