diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 206 |
1 files changed, 106 insertions, 100 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll index 36275ff12cf..ed9b8273fa4 100644 --- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll +++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll @@ -1,15 +1,15 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone -; SI-LABEL: {{^}}load_i8_to_f32: -; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]], -; SI-NOT: bfe -; SI-NOT: lshr -; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] -; SI: buffer_store_dword [[CONV]], +; GCN-LABEL: {{^}}load_i8_to_f32: +; GCN: buffer_load_ubyte [[LOADREG:v[0-9]+]], +; GCN-NOT: bfe +; GCN-NOT: lshr +; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] +; GCN: buffer_store_dword [[CONV]], define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { %load = load i8, i8 addrspace(1)* %in, align 1 %cvt = uitofp i8 %load to float @@ -17,11 +17,11 @@ define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* n ret void } -; SI-LABEL: {{^}}load_v2i8_to_v2f32: -; SI: buffer_load_ushort [[LD:v[0-9]+]] -; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]] -; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; GCN-LABEL: {{^}}load_v2i8_to_v2f32: +; GCN: buffer_load_ushort [[LD:v[0-9]+]] +; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]] +; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]] +; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind { %load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2 %cvt = uitofp <2 x i8> %load to <2 x float> @@ -29,13 +29,13 @@ define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> ret void } -; SI-LABEL: {{^}}load_v3i8_to_v3f32: -; SI: buffer_load_dword [[VAL:v[0-9]+]] -; SI-NOT: v_cvt_f32_ubyte3_e32 -; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]] -; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]] -; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; GCN-LABEL: {{^}}load_v3i8_to_v3f32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-NOT: v_cvt_f32_ubyte3_e32 +; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]] +; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]] +; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]] +; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind { %load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4 %cvt = uitofp <3 x i8> %load to <3 x float> @@ -43,15 +43,15 @@ define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> ret void } -; SI-LABEL: {{^}}load_v4i8_to_v4f32: -; SI: buffer_load_dword [[LOADREG:v[0-9]+]] -; SI-NOT: bfe -; SI-NOT: lshr -; SI-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] -; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]] -; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] -; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; GCN-LABEL: {{^}}load_v4i8_to_v4f32: +; GCN: buffer_load_dword [[LOADREG:v[0-9]+]] +; GCN-NOT: bfe +; GCN-NOT: lshr +; GCN-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] +; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]] +; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]] +; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] +; GCN: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 %cvt = uitofp <4 x i8> %load to <4 x float> @@ -63,19 +63,19 @@ define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> ; position in the word for the component. ; FIXME: Packing bytes -; SI-LABEL: {{^}}load_v4i8_to_v4f32_unaligned: -; SI: buffer_load_ubyte [[LOADREG3:v[0-9]+]] -; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]] -; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]] -; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]] -; SI-DAG: v_lshlrev_b32 -; SI-DAG: v_or_b32 -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], -; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, -; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]] - -; SI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}load_v4i8_to_v4f32_unaligned: +; GCN: buffer_load_ubyte [[LOADREG3:v[0-9]+]] +; GCN: buffer_load_ubyte [[LOADREG2:v[0-9]+]] +; GCN: buffer_load_ubyte [[LOADREG1:v[0-9]+]] +; GCN: buffer_load_ubyte [[LOADREG0:v[0-9]+]] +; GCN-DAG: v_lshlrev_b32 +; GCN-DAG: v_or_b32 +; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], +; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, +; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, +; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]] + +; GCN: buffer_store_dwordx4 define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <4 x i8> %load to <4 x float> @@ -85,25 +85,31 @@ define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out ; FIXME: Need to handle non-uniform case for function below (load without gep). ; Instructions still emitted to repack bytes for add use. -; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses: -; SI: {{buffer|flat}}_load_dword -; SI-DAG: v_cvt_f32_ubyte0_e32 -; SI-DAG: v_cvt_f32_ubyte1_e32 -; SI-DAG: v_cvt_f32_ubyte2_e32 -; SI-DAG: v_cvt_f32_ubyte3_e32 - -; SI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 24 -; SI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16 + +; GCN-LABEL: {{^}}load_v4i8_to_v4f32_2_uses: +; GCN: {{buffer|flat}}_load_dword +; GCN-DAG: v_cvt_f32_ubyte0_e32 +; GCN-DAG: v_cvt_f32_ubyte1_e32 +; GCN-DAG: v_cvt_f32_ubyte2_e32 +; GCN-DAG: v_cvt_f32_ubyte3_e32 + +; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 24 +; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16 + ; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16 ; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 8 ; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff, ; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff00, ; SI-DAG: v_add_i32 -; SI: {{buffer|flat}}_store_dwordx4 -; SI: {{buffer|flat}}_store_dword +; VI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffffff00, +; VI-DAG: v_add_u16_e32 +; VI-DAG: v_add_u16_e32 + +; GCN: {{buffer|flat}}_store_dwordx4 +; GCN: {{buffer|flat}}_store_dword -; SI: s_endpgm +; GCN: s_endpgm define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind { %tid.x = call i32 @llvm.amdgcn.workitem.id.x() %in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x @@ -116,8 +122,8 @@ define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, < } ; Make sure this doesn't crash. -; SI-LABEL: {{^}}load_v7i8_to_v7f32: -; SI: s_endpgm +; GCN-LABEL: {{^}}load_v7i8_to_v7f32: +; GCN: s_endpgm define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind { %load = load <7 x i8>, <7 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <7 x i8> %load to <7 x float> @@ -125,22 +131,22 @@ define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> ret void } -; SI-LABEL: {{^}}load_v8i8_to_v8f32: -; SI: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}}, -; SI-NOT: bfe -; SI-NOT: lshr -; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-NOT: bfe -; SI-NOT: lshr -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}load_v8i8_to_v8f32: +; GCN: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}}, +; GCN-NOT: bfe +; GCN-NOT: lshr +; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]] +; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]] +; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]] +; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]] +; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]] +; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]] +; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]] +; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]] +; GCN-NOT: bfe +; GCN-NOT: lshr +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind { %load = load <8 x i8>, <8 x i8> addrspace(1)* %in, align 8 %cvt = uitofp <8 x i8> %load to <8 x float> @@ -148,11 +154,11 @@ define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> ret void } -; SI-LABEL: {{^}}i8_zext_inreg_i32_to_f32: -; SI: buffer_load_dword [[LOADREG:v[0-9]+]], -; SI: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]] -; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] -; SI: buffer_store_dword [[CONV]], +; GCN-LABEL: {{^}}i8_zext_inreg_i32_to_f32: +; GCN: buffer_load_dword [[LOADREG:v[0-9]+]], +; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]] +; GCN-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] +; GCN: buffer_store_dword [[CONV]], define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %load = load i32, i32 addrspace(1)* %in, align 4 %add = add i32 %load, 2 @@ -162,7 +168,7 @@ define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addr ret void } -; SI-LABEL: {{^}}i8_zext_inreg_hi1_to_f32: +; GCN-LABEL: {{^}}i8_zext_inreg_hi1_to_f32: define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %load = load i32, i32 addrspace(1)* %in, align 4 %inreg = and i32 %load, 65280 @@ -174,7 +180,7 @@ define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addr ; We don't get these ones because of the zext, but instcombine removes ; them so it shouldn't really matter. -; SI-LABEL: {{^}}i8_zext_i32_to_f32: +; GCN-LABEL: {{^}}i8_zext_i32_to_f32: define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { %load = load i8, i8 addrspace(1)* %in, align 1 %ext = zext i8 %load to i32 @@ -183,7 +189,7 @@ define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1 ret void } -; SI-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32: +; GCN-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32: define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 %ext = zext <4 x i8> %load to <4 x i32> @@ -192,11 +198,11 @@ define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 ret void } -; SI-LABEL: {{^}}extract_byte0_to_f32: -; SI: buffer_load_dword [[VAL:v[0-9]+]] -; SI-NOT: [[VAL]] -; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] -; SI: buffer_store_dword [[CONV]] +; GCN-LABEL: {{^}}extract_byte0_to_f32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-NOT: [[VAL]] +; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] +; GCN: buffer_store_dword [[CONV]] define void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %val = load i32, i32 addrspace(1)* %in %and = and i32 %val, 255 @@ -205,11 +211,11 @@ define void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspac ret void } -; SI-LABEL: {{^}}extract_byte1_to_f32: -; SI: buffer_load_dword [[VAL:v[0-9]+]] -; SI-NOT: [[VAL]] -; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] -; SI: buffer_store_dword [[CONV]] +; GCN-LABEL: {{^}}extract_byte1_to_f32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-NOT: [[VAL]] +; GCN: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] +; GCN: buffer_store_dword [[CONV]] define void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %val = load i32, i32 addrspace(1)* %in %srl = lshr i32 %val, 8 @@ -219,11 +225,11 @@ define void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspac ret void } -; SI-LABEL: {{^}}extract_byte2_to_f32: -; SI: buffer_load_dword [[VAL:v[0-9]+]] -; SI-NOT: [[VAL]] -; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] -; SI: buffer_store_dword [[CONV]] +; GCN-LABEL: {{^}}extract_byte2_to_f32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-NOT: [[VAL]] +; GCN: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] +; GCN: buffer_store_dword [[CONV]] define void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %val = load i32, i32 addrspace(1)* %in %srl = lshr i32 %val, 16 @@ -233,11 +239,11 @@ define void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspac ret void } -; SI-LABEL: {{^}}extract_byte3_to_f32: -; SI: buffer_load_dword [[VAL:v[0-9]+]] -; SI-NOT: [[VAL]] -; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] -; SI: buffer_store_dword [[CONV]] +; GCN-LABEL: {{^}}extract_byte3_to_f32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-NOT: [[VAL]] +; GCN: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] +; GCN: buffer_store_dword [[CONV]] define void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %val = load i32, i32 addrspace(1)* %in %srl = lshr i32 %val, 24 |
