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-rw-r--r--llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll28
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
index a0857273e3e..916d667ec49 100644
--- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
+++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
@@ -447,6 +447,34 @@ done:
ret void
}
+%struct.foo = type { [3 x float], [3 x float] }
+
+; OPT-LABEL: @sink_ds_address(
+; OPT: ptrtoint %struct.foo addrspace(3)* %ptr to i64
+
+; GCN-LABEL: {{^}}sink_ds_address:
+; GCN: s_load_dword [[SREG1:s[0-9]+]],
+; GCN: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]]
+; GCN-DAG: ds_read2_b32 v[{{[0-9+:[0-9]+}}], [[VREG1]] offset0:3 offset1:5
+define void @sink_ds_address(%struct.foo addrspace(3)* nocapture %ptr) nounwind {
+entry:
+ %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0
+ %y = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2
+ br label %bb32
+
+bb32:
+ %a = load float, float addrspace(3)* %x, align 4
+ %b = load float, float addrspace(3)* %y, align 4
+ %cmp = fcmp one float %a, %b
+ br i1 %cmp, label %bb34, label %bb33
+
+bb33:
+ unreachable
+
+bb34:
+ unreachable
+}
+
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
attributes #0 = { nounwind readnone }
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