diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll b/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll index e515ca00d18..187320805c1 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll @@ -12,7 +12,7 @@ ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[0].X -define void @ngroups_x (i32 addrspace(1)* %out) { +define amdgpu_kernel void @ngroups_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.ngroups.x() #0 store i32 %0, i32 addrspace(1)* %out @@ -27,7 +27,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y -define void @ngroups_y (i32 addrspace(1)* %out) { +define amdgpu_kernel void @ngroups_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.ngroups.y() #0 store i32 %0, i32 addrspace(1)* %out @@ -42,7 +42,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z -define void @ngroups_z (i32 addrspace(1)* %out) { +define amdgpu_kernel void @ngroups_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.ngroups.z() #0 store i32 %0, i32 addrspace(1)* %out @@ -57,7 +57,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[0].W -define void @global_size_x (i32 addrspace(1)* %out) { +define amdgpu_kernel void @global_size_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.global.size.x() #0 store i32 %0, i32 addrspace(1)* %out @@ -72,7 +72,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[1].X -define void @global_size_y (i32 addrspace(1)* %out) { +define amdgpu_kernel void @global_size_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.global.size.y() #0 store i32 %0, i32 addrspace(1)* %out @@ -87,7 +87,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y -define void @global_size_z (i32 addrspace(1)* %out) { +define amdgpu_kernel void @global_size_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.global.size.z() #0 store i32 %0, i32 addrspace(1)* %out @@ -102,7 +102,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[1].Z -define void @local_size_x (i32 addrspace(1)* %out) { +define amdgpu_kernel void @local_size_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.local.size.x() #0 store i32 %0, i32 addrspace(1)* %out @@ -117,7 +117,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[1].W -define void @local_size_y (i32 addrspace(1)* %out) { +define amdgpu_kernel void @local_size_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.local.size.y() #0 store i32 %0, i32 addrspace(1)* %out @@ -132,7 +132,7 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV {{\*? *}}[[VAL]], KC0[2].X -define void @local_size_z (i32 addrspace(1)* %out) { +define amdgpu_kernel void @local_size_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.local.size.z() #0 store i32 %0, i32 addrspace(1)* %out @@ -153,7 +153,7 @@ entry: ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 -define void @tgid_x_legacy(i32 addrspace(1)* %out) { +define amdgpu_kernel void @tgid_x_legacy(i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tgid.x() #0 store i32 %0, i32 addrspace(1)* %out @@ -165,7 +165,7 @@ entry: ; GCN-NOHSA: buffer_store_dword [[VVAL]] ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 -define void @tgid_y_legacy(i32 addrspace(1)* %out) { +define amdgpu_kernel void @tgid_y_legacy(i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tgid.y() #0 store i32 %0, i32 addrspace(1)* %out @@ -181,7 +181,7 @@ entry: ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 -define void @tgid_z_legacy(i32 addrspace(1)* %out) { +define amdgpu_kernel void @tgid_z_legacy(i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tgid.z() #0 store i32 %0, i32 addrspace(1)* %out @@ -194,7 +194,7 @@ entry: ; FUNC-LABEL: {{^}}tidig_x_legacy: ; GCN-NOHSA: buffer_store_dword v0 -define void @tidig_x_legacy(i32 addrspace(1)* %out) { +define amdgpu_kernel void @tidig_x_legacy(i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tidig.x() #0 store i32 %0, i32 addrspace(1)* %out @@ -208,7 +208,7 @@ entry: ; FUNC-LABEL: {{^}}tidig_y_legacy: ; GCN-NOHSA: buffer_store_dword v1 -define void @tidig_y_legacy(i32 addrspace(1)* %out) { +define amdgpu_kernel void @tidig_y_legacy(i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tidig.y() #0 store i32 %0, i32 addrspace(1)* %out @@ -221,7 +221,7 @@ entry: ; FUNC-LABEL: {{^}}tidig_z_legacy: ; GCN-NOHSA: buffer_store_dword v2 -define void @tidig_z_legacy(i32 addrspace(1)* %out) { +define amdgpu_kernel void @tidig_z_legacy(i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tidig.z() #0 store i32 %0, i32 addrspace(1)* %out |
