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-rw-r--r--llvm/test/CodeGen/AArch64/uadd_sat_plus.ll73
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diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll b/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
new file mode 100644
index 00000000000..2989fc5b754
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+++ b/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+declare i4 @llvm.uadd.sat.i4(i4, i4)
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-LABEL: func32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: adds w8, w0, w8
+; CHECK-NEXT: csinv w0, w8, wzr, lo
+; CHECK-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-LABEL: func64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adds x8, x0, x2
+; CHECK-NEXT: csinv x0, x8, xzr, lo
+; CHECK-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; CHECK-LABEL: func16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #16
+; CHECK-NEXT: adds w8, w9, w8, lsl #16
+; CHECK-NEXT: csinv w8, w8, wzr, lo
+; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #24
+; CHECK-NEXT: adds w8, w9, w8, lsl #24
+; CHECK-NEXT: csinv w8, w8, wzr, lo
+; CHECK-NEXT: lsr w0, w8, #24
+; CHECK-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #28
+; CHECK-NEXT: adds w8, w9, w8, lsl #28
+; CHECK-NEXT: csinv w8, w8, wzr, lo
+; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
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