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-rw-r--r--llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll125
1 files changed, 40 insertions, 85 deletions
diff --git a/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
index 20c5efcf7f3..7e78d11f6d8 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
@@ -37,27 +37,16 @@ define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_allones_eq:
; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI1_0
-; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT: adrp x8, .LCPI1_1
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_1]
-; CHECK-NEXT: adrp x8, .LCPI1_2
-; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI1_2]
-; CHECK-NEXT: adrp x8, .LCPI1_3
-; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
-; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
-; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI1_3]
-; CHECK-NEXT: adrp x8, .LCPI1_4
-; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_4]
-; CHECK-NEXT: neg v3.4s, v3.4s
-; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
-; CHECK-NEXT: ushr v1.4s, v1.4s, #31
-; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: adrp x10, .LCPI1_0
+; CHECK-NEXT: mov w8, #52429
+; CHECK-NEXT: mov w9, #39321
+; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI1_0]
+; CHECK-NEXT: movk w8, #52428, lsl #16
+; CHECK-NEXT: movk w9, #6553, lsl #16
+; CHECK-NEXT: dup v2.4s, w8
+; CHECK-NEXT: dup v3.4s, w9
+; CHECK-NEXT: mla v3.4s, v0.4s, v2.4s
+; CHECK-NEXT: cmhs v0.4s, v1.4s, v3.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
@@ -69,28 +58,16 @@ define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_allones_ne:
; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI2_0
-; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: adrp x8, .LCPI2_1
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_1]
-; CHECK-NEXT: adrp x8, .LCPI2_2
-; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_2]
-; CHECK-NEXT: adrp x8, .LCPI2_3
-; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
-; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
-; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI2_3]
-; CHECK-NEXT: adrp x8, .LCPI2_4
-; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_4]
-; CHECK-NEXT: neg v3.4s, v3.4s
-; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
-; CHECK-NEXT: ushr v1.4s, v1.4s, #31
-; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-NEXT: mvn v0.16b, v0.16b
+; CHECK-NEXT: adrp x10, .LCPI2_0
+; CHECK-NEXT: mov w8, #52429
+; CHECK-NEXT: mov w9, #39321
+; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI2_0]
+; CHECK-NEXT: movk w8, #52428, lsl #16
+; CHECK-NEXT: movk w9, #6553, lsl #16
+; CHECK-NEXT: dup v2.4s, w8
+; CHECK-NEXT: dup v3.4s, w9
+; CHECK-NEXT: mla v3.4s, v0.4s, v2.4s
+; CHECK-NEXT: cmhi v0.4s, v3.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
@@ -327,27 +304,16 @@ define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_one:
; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI10_0
-; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI10_0]
-; CHECK-NEXT: adrp x8, .LCPI10_1
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_1]
-; CHECK-NEXT: adrp x8, .LCPI10_2
-; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI10_2]
-; CHECK-NEXT: adrp x8, .LCPI10_3
-; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
-; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
-; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI10_3]
-; CHECK-NEXT: adrp x8, .LCPI10_4
-; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_4]
-; CHECK-NEXT: neg v3.4s, v3.4s
-; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
-; CHECK-NEXT: ushr v1.4s, v1.4s, #31
-; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: adrp x10, .LCPI10_0
+; CHECK-NEXT: mov w8, #52429
+; CHECK-NEXT: mov w9, #39321
+; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI10_0]
+; CHECK-NEXT: movk w8, #52428, lsl #16
+; CHECK-NEXT: movk w9, #6553, lsl #16
+; CHECK-NEXT: dup v2.4s, w8
+; CHECK-NEXT: dup v3.4s, w9
+; CHECK-NEXT: mla v3.4s, v0.4s, v2.4s
+; CHECK-NEXT: cmhs v0.4s, v1.4s, v3.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
@@ -625,27 +591,16 @@ define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwi
define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_allones_and_one:
; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI19_0
-; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
-; CHECK-NEXT: adrp x8, .LCPI19_1
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_1]
-; CHECK-NEXT: adrp x8, .LCPI19_2
-; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI19_2]
-; CHECK-NEXT: adrp x8, .LCPI19_3
-; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
-; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
-; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI19_3]
-; CHECK-NEXT: adrp x8, .LCPI19_4
-; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_4]
-; CHECK-NEXT: neg v3.4s, v3.4s
-; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
-; CHECK-NEXT: ushr v1.4s, v1.4s, #31
-; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: adrp x10, .LCPI19_0
+; CHECK-NEXT: mov w8, #52429
+; CHECK-NEXT: mov w9, #39321
+; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI19_0]
+; CHECK-NEXT: movk w8, #52428, lsl #16
+; CHECK-NEXT: movk w9, #6553, lsl #16
+; CHECK-NEXT: dup v2.4s, w8
+; CHECK-NEXT: dup v3.4s, w9
+; CHECK-NEXT: mla v3.4s, v0.4s, v2.4s
+; CHECK-NEXT: cmhs v0.4s, v1.4s, v3.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
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