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-rw-r--r--llvm/test/CodeGen/AArch64/postra-mi-sched.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AArch64/postra-mi-sched.ll b/llvm/test/CodeGen/AArch64/postra-mi-sched.ll
index 5a407246609..e7f3f5515a7 100644
--- a/llvm/test/CodeGen/AArch64/postra-mi-sched.ll
+++ b/llvm/test/CodeGen/AArch64/postra-mi-sched.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O3 -march=aarch64 -mcpu=cortex-a53 | FileCheck %s
+; RUN: llc < %s -O3 -mtriple=aarch64-eabi -mcpu=cortex-a53 | FileCheck %s
; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
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