diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll | 16 | 
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll index 1af2bd10912..eafc5d9df7f 100644 --- a/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll +++ b/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll @@ -11,8 +11,8 @@ define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {  ; CHECK-DAG: fcvtn v1.4h, [[S2]]  ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]  ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]] -; CHECK-DAg: ins v0.d[1], v[[R1]].d[0] -; CHECK-DAG: ins v1.d[1], v[[R3]].d[0] +; CHECK-DAG: mov v0.d[1], v[[R1]].d[0] +; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]    %1 = sitofp <16 x i32> %a to <16 x half>    ret <16 x half> %1 @@ -44,8 +44,8 @@ define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {  ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s  ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s  ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s -; CHECK-DAG: ins v0.d[1], v[[R1]].d[0] -; CHECK-DAG: ins v1.d[1], v[[R3]].d[0] +; CHECK-DAG: mov v0.d[1], v[[R1]].d[0] +; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]    %1 = sitofp <16 x i64> %a to <16 x half>    ret <16 x half> %1 @@ -62,8 +62,8 @@ define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {  ; CHECK-DAG: fcvtn v1.4h, [[S2]]  ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]  ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]] -; CHECK-DAg: ins v0.d[1], v[[R1]].d[0] -; CHECK-DAG: ins v1.d[1], v[[R3]].d[0] +; CHECK-DAG: mov v0.d[1], v[[R1]].d[0] +; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]    %1 = uitofp <16 x i32> %a to <16 x half>    ret <16 x half> %1 @@ -95,8 +95,8 @@ define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {  ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s  ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s  ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s -; CHECK-DAG: ins v0.d[1], v[[R1]].d[0] -; CHECK-DAG: ins v1.d[1], v[[R3]].d[0] +; CHECK-DAG: mov v0.d[1], v[[R1]].d[0] +; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]    %1 = uitofp <16 x i64> %a to <16 x half>    ret <16 x half> %1  | 

