diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-atomic-128.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-atomic-128.ll | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll index 21e3c768ee6..622d5172a2c 100644 --- a/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll +++ b/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll @@ -29,7 +29,8 @@ define void @fetch_and_nand(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw nand i128* %p, i128 %bits release store i128 %val, i128* @var, align 16 ret void @@ -44,7 +45,8 @@ define void @fetch_and_or(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw or i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -59,7 +61,8 @@ define void @fetch_and_add(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw add i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -74,7 +77,8 @@ define void @fetch_and_sub(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw sub i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -95,7 +99,8 @@ define void @fetch_and_min(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw min i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -116,7 +121,8 @@ define void @fetch_and_max(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw max i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -137,7 +143,8 @@ define void @fetch_and_umin(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw umin i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -158,7 +165,8 @@ define void @fetch_and_umax(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] +; CHECK-DAG: str [[DEST_REGLO]], [{{.*}}, :lo12:var] +; CHECK-DAG: str [[DEST_REGHI]], [{{.*}}, :lo12:var+8] %val = atomicrmw umax i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void |
