1 files changed, 16 insertions, 15 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
index 16f8d016063..6da76792163 100644
--- a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll
@@ -5,31 +5,32 @@
 
 ; base + offset (imm9)
 ; CHECK: @t1
-; CHECK: ldr xzr, [x0, #8]
+; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
 ; CHECK: ret
-define void @t1(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 1
+define void @t1() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 1
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + offset (> imm9)
 ; CHECK: @t2
-; CHECK: sub [[ADDREG:x[0-9]+]], x0, #264
+; CHECK: sub [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #264
 ; CHECK: ldr xzr, [
+; CHECK: [[ADDREG]]]
 ; CHECK: ret
-define void @t2(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 -33
+define void @t2() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 -33
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
 ; CHECK: @t3
-; CHECK: ldr xzr, [x0, #32760]
+; CHECK: ldr xzr, [x{{[0-9]+}}, #32760]
 ; CHECK: ret
-define void @t3(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4095
+define void @t3() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4095
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
@@ -37,10 +38,10 @@ define void @t3(i64* %object) {
 ; base + unsigned offset (> imm12 * size of type in bytes)
 ; CHECK: @t4
 ; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
-; CHECK: ldr xzr, [x0, x[[NUM]]]
+; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
-define void @t4(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4096
+define void @t4() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4096
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
@@ -57,12 +58,12 @@ define void @t5(i64 %a) {
 
 ; base + reg + imm
 ; CHECK: @t6
-; CHECK: add [[ADDREG:x[0-9]+]], x1, x0, lsl #3
+; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3
 ; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
-define void @t6(i64 %a, i64* %object) {
-  %tmp1 = getelementptr inbounds i64, i64* %object, i64 %a
+define void @t6(i64 %a) {
+  %tmp1 = getelementptr inbounds i64, i64* @object, i64 %a
   %incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void