diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir new file mode 100644 index 00000000000..6abe3017e46 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + + define void @zextload_s32_from_s16(i16 *%addr) { ret void } + define void @zextload_s32_from_s16_not_combined(i16 *%addr) { ret void } +... + +--- +name: zextload_s32_from_s16 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x0 + + ; CHECK-LABEL: name: zextload_s32_from_s16 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) + ; CHECK: $w0 = COPY [[T0]] + %0:gpr(p0) = COPY $x0 + %1:gpr(s32) = G_ZEXTLOAD %0 :: (load 2 from %ir.addr) + $w0 = COPY %1(s32) +... +--- +name: zextload_s32_from_s16_not_combined +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x0 + + ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) + ; CHECK: [[T1:%[0-9]+]]:gpr32 = UBFMWri [[T0]], 0, 15 + ; CHECK: $w0 = COPY [[T1]] + %0:gpr(p0) = COPY $x0 + %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr) + %2:gpr(s32) = G_ZEXT %1 + $w0 = COPY %2(s32) +... |
