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-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp17
-rw-r--r--llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp4
2 files changed, 14 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 76ed383ac3f..72cc47da7c5 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -323,18 +323,25 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << ":\n";
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- if (!livein_empty()) {
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
+ if (!livein_empty() && MRI.tracksLiveness()) {
if (Indexes) OS << '\t';
- OS << " Live Ins:";
- for (const auto &LI : LiveIns) {
- OS << ' ' << printReg(LI.PhysReg, TRI);
+ OS.indent(2) << "liveins: ";
+
+ bool First = true;
+ for (const auto &LI : liveins()) {
+ if (!First)
+ OS << ", ";
+ First = false;
+ OS << printReg(LI.PhysReg, TRI);
if (!LI.LaneMask.all())
- OS << ':' << PrintLaneMask(LI.LaneMask);
+ OS << ":0x" << PrintLaneMask(LI.LaneMask);
}
OS << '\n';
}
if (!succ_empty()) {
+ if (Indexes) OS << '\t';
// Print the successors
OS.indent(2) << "successors: ";
for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
diff --git a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
index 32d801b13de..347f66d1709 100644
--- a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
+++ b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
@@ -60,7 +60,7 @@ namespace llvm {
/// expands to the following machine code:
///
/// %bb.0: derived from LLVM BB %entry
-/// Live Ins: %f1 %f3 %x6
+/// liveins: %f1 %f3 %x6
/// <SNIP1>
/// %0 = COPY %f1; F8RC:%0
/// %5 = CMPLWI killed %4, 0; CRRC:%5 GPRC:%4
@@ -98,7 +98,7 @@ namespace llvm {
/// If all conditions are meet, IR should collapse to:
///
/// %bb.0: derived from LLVM BB %entry
-/// Live Ins: %f1 %f3 %x6
+/// liveins: %f1 %f3 %x6
/// <SNIP1>
/// %0 = COPY %f1; F8RC:%0
/// %5 = CMPLWI killed %4, 0; CRRC:%5 GPRC:%4
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