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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp8
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h4
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h37
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h9
-rw-r--r--llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp79
-rw-r--r--llvm/lib/Target/AMDGPU/R600ISelLowering.cpp40
-rw-r--r--llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp4
-rw-r--r--llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h7
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstructions.td7
10 files changed, 15 insertions, 182 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index c9c95c796a6..7a9b160f213 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -95,6 +95,10 @@ AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)) {}
+const char *AMDGPUAsmPrinter::getPassName() const {
+ return "AMDGPU Assembly Printer";
+}
+
void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
return;
@@ -229,7 +233,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
} else {
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
OutStreamer->emitRawComment(
- Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
+ Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
}
}
@@ -301,7 +305,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
OutStreamer->EmitIntValue(RsrcReg, 4);
OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
- S_STACK_SIZE(MFI->StackSize), 4);
+ S_STACK_SIZE(MFI->CFStackSize), 4);
OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
index 7b04c539520..270d3bfcf9d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -108,9 +108,7 @@ public:
bool runOnMachineFunction(MachineFunction &MF) override;
- const char *getPassName() const override {
- return "AMDGPU Assembly Printer";
- }
+ const char *getPassName() const override;
/// Implemented in AMDGPUMCInstLower.cpp
void EmitInstruction(const MachineInstr *MI) override;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 3fe61aa449e..5a7485bc6b1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -116,10 +116,10 @@ public:
AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
StringRef GPU, StringRef FS);
- const AMDGPUInstrInfo *getInstrInfo() const override;
- const AMDGPUFrameLowering *getFrameLowering() const override;
- const AMDGPUTargetLowering *getTargetLowering() const override;
- const AMDGPURegisterInfo *getRegisterInfo() const override;
+ const AMDGPUInstrInfo *getInstrInfo() const override = 0;
+ const AMDGPUFrameLowering *getFrameLowering() const override = 0;
+ const AMDGPUTargetLowering *getTargetLowering() const override = 0;
+ const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins;
@@ -428,35 +428,6 @@ public:
}
};
-
-inline const AMDGPUInstrInfo *AMDGPUSubtarget::getInstrInfo() const {
- if (getGeneration() >= SOUTHERN_ISLANDS)
- return static_cast<const SISubtarget *>(this)->getInstrInfo();
-
- return static_cast<const R600Subtarget *>(this)->getInstrInfo();
-}
-
-inline const AMDGPUFrameLowering *AMDGPUSubtarget::getFrameLowering() const {
- if (getGeneration() >= SOUTHERN_ISLANDS)
- return static_cast<const SISubtarget *>(this)->getFrameLowering();
-
- return static_cast<const R600Subtarget *>(this)->getFrameLowering();
-}
-
-inline const AMDGPUTargetLowering *AMDGPUSubtarget::getTargetLowering() const {
- if (getGeneration() >= SOUTHERN_ISLANDS)
- return static_cast<const SISubtarget *>(this)->getTargetLowering();
-
- return static_cast<const R600Subtarget *>(this)->getTargetLowering();
-}
-
-inline const AMDGPURegisterInfo *AMDGPUSubtarget::getRegisterInfo() const {
- if (getGeneration() >= SOUTHERN_ISLANDS)
- return static_cast<const SISubtarget *>(this)->getRegisterInfo();
-
- return static_cast<const R600Subtarget *>(this)->getRegisterInfo();
-}
-
} // End namespace llvm
#endif
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index b0eb3a9a15f..d8a71b464cc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -40,7 +40,7 @@ public:
~AMDGPUTargetMachine();
const AMDGPUSubtarget *getSubtargetImpl() const;
- const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override;
+ const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override = 0;
const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
return &IntrinsicInfo;
@@ -90,13 +90,6 @@ public:
const SISubtarget *getSubtargetImpl(const Function &) const override;
};
-inline const AMDGPUSubtarget *AMDGPUTargetMachine::getSubtargetImpl(
- const Function &F) const {
- if (getTargetTriple().getArch() == Triple::amdgcn)
- return static_cast<const GCNTargetMachine *>(this)->getSubtargetImpl(F);
- return static_cast<const R600TargetMachine *>(this)->getSubtargetImpl(F);
-}
-
} // End namespace llvm
#endif
diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
index d5bda4a8303..4e106bd732c 100644
--- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
@@ -680,7 +680,7 @@ public:
.addImm(Alu->getOperand(8).getImm());
Alu->eraseFromParent();
}
- MFI->StackSize = CFStack.MaxStackSize;
+ MFI->CFStackSize = CFStack.MaxStackSize;
}
return false;
diff --git a/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp b/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
index 0385b6283f3..284900f32a0 100644
--- a/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
@@ -116,85 +116,6 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
MI.eraseFromParent();
continue;
}
-
- case AMDGPU::INTERP_PAIR_XY: {
- MachineInstr *BMI;
- unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
- MI.getOperand(2).getImm());
-
- for (unsigned Chan = 0; Chan < 4; ++Chan) {
- unsigned DstReg;
-
- if (Chan < 2)
- DstReg = MI.getOperand(Chan).getReg();
- else
- DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
-
- BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
- DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
-
- if (Chan > 0) {
- BMI->bundleWithPred();
- }
- if (Chan >= 2)
- TII->addFlag(*BMI, 0, MO_FLAG_MASK);
- if (Chan != 3)
- TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
- }
-
- MI.eraseFromParent();
- continue;
- }
-
- case AMDGPU::INTERP_PAIR_ZW: {
- MachineInstr *BMI;
- unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
- MI.getOperand(2).getImm());
-
- for (unsigned Chan = 0; Chan < 4; ++Chan) {
- unsigned DstReg;
-
- if (Chan < 2)
- DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
- else
- DstReg = MI.getOperand(Chan-2).getReg();
-
- BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
- DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
-
- if (Chan > 0) {
- BMI->bundleWithPred();
- }
- if (Chan < 2)
- TII->addFlag(*BMI, 0, MO_FLAG_MASK);
- if (Chan != 3)
- TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
- }
-
- MI.eraseFromParent();
- continue;
- }
-
- case AMDGPU::INTERP_VEC_LOAD: {
- const R600RegisterInfo &TRI = TII->getRegisterInfo();
- MachineInstr *BMI;
- unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
- MI.getOperand(1).getImm());
- unsigned DstReg = MI.getOperand(0).getReg();
-
- for (unsigned Chan = 0; Chan < 4; ++Chan) {
- BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
- TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
- if (Chan > 0) {
- BMI->bundleWithPred();
- }
- if (Chan != 3)
- TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
- }
-
- MI.eraseFromParent();
- continue;
- }
case AMDGPU::DOT_4: {
const R600RegisterInfo &TRI = TII->getRegisterInfo();
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 8ccd176930a..f9ceb8e1407 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -592,12 +592,6 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
break;
}
case AMDGPU::RETURN: {
- // RETURN instructions must have the live-out registers as implicit uses,
- // otherwise they appear dead.
- R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
- MachineInstrBuilder MIB(*MF, MI);
- for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
- MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
return BB;
}
}
@@ -671,15 +665,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
switch(IntrinsicID) {
default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
case AMDGPUIntrinsic::r600_tex:
- case AMDGPUIntrinsic::r600_texc:
- case AMDGPUIntrinsic::r600_txl:
- case AMDGPUIntrinsic::r600_txlc:
- case AMDGPUIntrinsic::r600_txb:
- case AMDGPUIntrinsic::r600_txbc:
- case AMDGPUIntrinsic::r600_txf:
- case AMDGPUIntrinsic::r600_txq:
- case AMDGPUIntrinsic::r600_ddx:
- case AMDGPUIntrinsic::r600_ddy: {
+ case AMDGPUIntrinsic::r600_texc: {
unsigned TextureOp;
switch (IntrinsicID) {
case AMDGPUIntrinsic::r600_tex:
@@ -688,30 +674,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
case AMDGPUIntrinsic::r600_texc:
TextureOp = 1;
break;
- case AMDGPUIntrinsic::r600_txl:
- TextureOp = 2;
- break;
- case AMDGPUIntrinsic::r600_txlc:
- TextureOp = 3;
- break;
- case AMDGPUIntrinsic::r600_txb:
- TextureOp = 4;
- break;
- case AMDGPUIntrinsic::r600_txbc:
- TextureOp = 5;
- break;
- case AMDGPUIntrinsic::r600_txf:
- TextureOp = 6;
- break;
- case AMDGPUIntrinsic::r600_txq:
- TextureOp = 7;
- break;
- case AMDGPUIntrinsic::r600_ddx:
- TextureOp = 8;
- break;
- case AMDGPUIntrinsic::r600_ddy:
- TextureOp = 9;
- break;
default:
llvm_unreachable("Unknow Texture Operation");
}
diff --git a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
index 01105c614c5..3ca319c6c6c 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
@@ -12,9 +12,5 @@
using namespace llvm;
-
-// Pin the vtable to this file.
-void R600MachineFunctionInfo::anchor() {}
-
R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
: AMDGPUMachineFunction(MF) { }
diff --git a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
index 04a4436ebe0..29ac0920f99 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
@@ -14,18 +14,13 @@
#define LLVM_LIB_TARGET_AMDGPU_R600MACHINEFUNCTIONINFO_H
#include "AMDGPUMachineFunction.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include <vector>
namespace llvm {
class R600MachineFunctionInfo final : public AMDGPUMachineFunction {
- void anchor() override;
public:
R600MachineFunctionInfo(const MachineFunction &MF);
- SmallVector<unsigned, 4> LiveOuts;
- std::vector<unsigned> IndirectRegs;
- unsigned StackSize;
+ unsigned CFStackSize;
};
} // End llvm namespace
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 514f2f5e35a..944248a7fdd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -11,13 +11,6 @@
// that are not yet supported remain commented out.
//===----------------------------------------------------------------------===//
-class InterpSlots {
-int P0 = 2;
-int P10 = 0;
-int P20 = 1;
-}
-def INTERP : InterpSlots;
-
def isGCN : Predicate<"Subtarget->getGeneration() "
">= SISubtarget::SOUTHERN_ISLANDS">,
AssemblerPredicate<"FeatureGCN">;
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