diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFPStack.td | 28 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 2 |
4 files changed, 25 insertions, 24 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 4c581083d26..83c053c8f11 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -1114,7 +1114,8 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, } // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. - if (RegNo == X86::ST0) { + if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) { + RegNo = X86::ST0; Parser.Lex(); // Eat 'st' // Check to see if we have '(4)' after %st. diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td index a82645d1653..d044fa2daa8 100644 --- a/llvm/lib/Target/X86/X86InstrFPStack.td +++ b/llvm/lib/Target/X86/X86InstrFPStack.td @@ -268,13 +268,13 @@ class FPrST0PInst<Format fp, string asm> // we have to put some 'r's in and take them out of weird places. let SchedRW = [WriteFAdd], Defs = [FPSW] in { def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; -def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; +def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; -def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; +def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; -def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; +def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; } // SchedRW let SchedRW = [WriteFCom], Defs = [FPSW] in { @@ -283,15 +283,15 @@ def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; } // SchedRW let SchedRW = [WriteFMul], Defs = [FPSW] in { def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; -def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; +def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; } // SchedRW let SchedRW = [WriteFDiv], Defs = [FPSW] in { def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; -def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; +def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; -def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; +def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; } // SchedRW @@ -398,21 +398,21 @@ defm CMOVNP : FPCMov<X86_COND_NP>; let Predicates = [HasCMov] in { // These are not factored because there's no clean way to pass DA/DB. def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op), - "fcmovb\t{$op, %st|st, $op}">; + "fcmovb\t{$op, %st(0)|st(0), $op}">; def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op), - "fcmovbe\t{$op, %st|st, $op}">; + "fcmovbe\t{$op, %st(0)|st(0), $op}">; def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), - "fcmove\t{$op, %st|st, $op}">; + "fcmove\t{$op, %st(0)|st(0), $op}">; def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op), - "fcmovu\t{$op, %st|st, $op}">; + "fcmovu\t{$op, %st(0)|st(0), $op}">; def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op), - "fcmovnb\t{$op, %st|st, $op}">; + "fcmovnb\t{$op, %st(0)|st(0), $op}">; def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op), - "fcmovnbe\t{$op, %st|st, $op}">; + "fcmovnbe\t{$op, %st(0)|st(0), $op}">; def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), - "fcmovne\t{$op, %st|st, $op}">; + "fcmovne\t{$op, %st(0)|st(0), $op}">; def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op), - "fcmovnu\t{$op, %st|st, $op}">; + "fcmovnu\t{$op, %st(0)|st(0), $op}">; } // Predicates = [HasCMov] } // SchedRW diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 373b516e598..9376dc2049c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3238,9 +3238,9 @@ def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with // gas. multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { - def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st|st, $op}"), + def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), (Inst RST:$op), EmitAlias>; - def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"), + def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), (Inst ST0), EmitAlias>; } @@ -3265,12 +3265,12 @@ defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, // solely because gas supports it. -def : InstAlias<"faddp\t{%st, $op|$op, st}", (ADD_FPrST0 RST:$op)>; -def : InstAlias<"fmulp\t{%st, $op|$op, st}", (MUL_FPrST0 RST:$op)>; -def : InstAlias<"fsub{|r}p\t{%st, $op|$op, st}", (SUBR_FPrST0 RST:$op)>; -def : InstAlias<"fsub{r|}p\t{%st, $op|$op, st}", (SUB_FPrST0 RST:$op)>; -def : InstAlias<"fdiv{|r}p\t{%st, $op|$op, st}", (DIVR_FPrST0 RST:$op)>; -def : InstAlias<"fdiv{r|}p\t{%st, $op|$op, st}", (DIV_FPrST0 RST:$op)>; +def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op)>; +def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index d671d0a998f..e3abe1f1c3a 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -277,7 +277,7 @@ def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; // pseudo registers, but we still mark them as aliasing FP registers. That // way both kinds can be live without exceeding the stack depth. ST registers // are only live around inline assembly. -def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; +def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>; def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; |
