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-rw-r--r--llvm/lib/Target/Mips/MipsLegalizerInfo.cpp15
1 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index d4de79c10a2..80a24a3ab42 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -219,8 +219,16 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
return true;
}
-bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
+bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const {
+ const MipsSubtarget &ST =
+ static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
+ const MipsInstrInfo &TII = *ST.getInstrInfo();
+ const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
+ const RegisterBankInfo &RBI = *ST.getRegBankInfo();
+ MIRBuilder.setInstr(MI);
+
switch (MI.getIntrinsicID()) {
case Intrinsic::memcpy:
case Intrinsic::memset:
@@ -230,6 +238,11 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo
return false;
MI.eraseFromParent();
return true;
+ case Intrinsic::trap: {
+ MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
+ MI.eraseFromParent();
+ return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
+ }
default:
break;
}
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