diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SplitKit.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 |
3 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 323045fd2aa..aaaa342b520 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -552,7 +552,7 @@ SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg, if ((SubRegMask & ~LaneMask).any()) continue; - unsigned PopCount = countPopulation(SubRegMask.getAsInteger()); + unsigned PopCount = SubRegMask.getNumLanes(); PossibleIndexes.push_back(Idx); if (PopCount > BestCover) { BestCover = PopCount; @@ -583,8 +583,8 @@ SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg, // Try to cover as much of the remaining lanes as possible but // as few of the already covered lanes as possible. - int Cover = countPopulation((SubRegMask & LanesLeft).getAsInteger()) - - countPopulation((SubRegMask & ~LanesLeft).getAsInteger()); + int Cover = (SubRegMask & LanesLeft).getNumLanes() + - (SubRegMask & ~LanesLeft).getNumLanes(); if (Cover > BestCover) { BestCover = Cover; BestIdx = Idx; diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp index 09cac8c2c8f..0384340174f 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -107,7 +107,7 @@ void GCNRegPressure::inc(unsigned Reg, assert(PrevMask < NewMask); Value[Kind == SGPR_TUPLE ? SGPR32 : VGPR32] += - Sign * countPopulation((~PrevMask & NewMask).getAsInteger()); + Sign * (~PrevMask & NewMask).getNumLanes(); if (PrevMask.none()) { assert(NewMask.any()); diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 4a3fbb4593b..d9a5ce338bf 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1275,8 +1275,7 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass( return RC; // We can assume that each lane corresponds to one 32-bit register. - LaneBitmask::Type Mask = getSubRegIndexLaneMask(SubIdx).getAsInteger(); - unsigned Count = countPopulation(Mask); + unsigned Count = getSubRegIndexLaneMask(SubIdx).getNumLanes(); if (isSGPRClass(RC)) { switch (Count) { case 1: |
