diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsConstantIslandPass.cpp | 3 |
5 files changed, 12 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 0fd5bb5897c..1d961af70de 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -353,8 +353,8 @@ void FastISel::recomputeInsertPt() { void FastISel::removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E) { - assert(static_cast<MachineInstr *>(I) && static_cast<MachineInstr *>(E) && - std::distance(I, E) > 0 && "Invalid iterator!"); + assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 && + "Invalid iterator!"); while (I != E) { MachineInstr *Dead = &*I; ++I; diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp index 21de76396b1..94a5355c916 100644 --- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -423,25 +423,21 @@ bool AMDGPUCFGStructurizer::needMigrateBlock(MachineBasicBlock *MBB) const { void AMDGPUCFGStructurizer::reversePredicateSetter( MachineBasicBlock::iterator I) { - assert(static_cast<MachineInstr *>(I) && "Expected valid iterator"); + assert(I.isValid() && "Expected valid iterator"); for (;; --I) { if (I->getOpcode() == AMDGPU::PRED_X) { - switch (static_cast<MachineInstr *>(I)->getOperand(2).getImm()) { + switch (I->getOperand(2).getImm()) { case OPCODE_IS_ZERO_INT: - static_cast<MachineInstr *>(I)->getOperand(2) - .setImm(OPCODE_IS_NOT_ZERO_INT); + I->getOperand(2).setImm(OPCODE_IS_NOT_ZERO_INT); return; case OPCODE_IS_NOT_ZERO_INT: - static_cast<MachineInstr *>(I)->getOperand(2) - .setImm(OPCODE_IS_ZERO_INT); + I->getOperand(2).setImm(OPCODE_IS_ZERO_INT); return; case OPCODE_IS_ZERO: - static_cast<MachineInstr *>(I)->getOperand(2) - .setImm(OPCODE_IS_NOT_ZERO); + I->getOperand(2).setImm(OPCODE_IS_NOT_ZERO); return; case OPCODE_IS_NOT_ZERO: - static_cast<MachineInstr *>(I)->getOperand(2) - .setImm(OPCODE_IS_ZERO); + I->getOperand(2).setImm(OPCODE_IS_ZERO); return; default: llvm_unreachable("PRED_X Opcode invalid!"); diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 08b95a5be64..573b18744ba 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -665,7 +665,7 @@ bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB, // handled if (isBranch(I->getOpcode())) return true; - if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) { + if (!isJump(I->getOpcode())) { return false; } @@ -680,8 +680,7 @@ bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB, // If there is only one terminator instruction, process it. unsigned LastOpc = LastInst.getOpcode(); - if (I == MBB.begin() || - !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) { + if (I == MBB.begin() || !isJump((--I)->getOpcode())) { if (LastOpc == AMDGPU::JUMP) { TBB = LastInst.getOperand(0).getMBB(); return false; diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index bcebf5d034c..361bba7f878 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -606,7 +606,7 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2, for (auto NewMI : DbgMItoMove) { // If iterator MI is pointing to DEBUG_VAL, make sure // MI now points to next relevant instruction. - if (NewMI == (MachineInstr*)MI) + if (NewMI == MI) ++MI; BB->splice(InsertPt, BB, NewMI); } diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 6531b32594f..cbc5e4bdd4e 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -1301,8 +1301,7 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, Offset < BaseInsertOffset; Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) { assert(MI != UserMBB->end() && "Fell off end of block"); - if (CPUIndex < NumCPUsers && - CPUsers[CPUIndex].MI == static_cast<MachineInstr *>(MI)) { + if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) { CPUser &U = CPUsers[CPUIndex]; if (!isOffsetInRange(Offset, EndInsertOffset, U)) { // Shift intertion point by one unit of alignment so it is within reach. |
