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-rw-r--r--llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp28
-rw-r--r--llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h3
2 files changed, 31 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index c2204af533c..a626323635c 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -884,3 +884,31 @@ bool AArch64TTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
}
return false;
}
+
+int AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy,
+ bool IsPairwiseForm) {
+
+ if (IsPairwiseForm)
+ return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwiseForm);
+
+ std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
+ MVT MTy = LT.second;
+ int ISD = TLI->InstructionOpcodeToISD(Opcode);
+ assert(ISD && "Invalid opcode");
+
+ // Horizontal adds can use the 'addv' instruction. We model the cost of these
+ // instructions as normal vector adds. This is the only arithmetic vector
+ // reduction operation for which we have an instruction.
+ static const CostTblEntry CostTblNoPairwise[]{
+ {ISD::ADD, MVT::v8i8, 1},
+ {ISD::ADD, MVT::v16i8, 1},
+ {ISD::ADD, MVT::v4i16, 1},
+ {ISD::ADD, MVT::v8i16, 1},
+ {ISD::ADD, MVT::v4i32, 1},
+ };
+
+ if (const auto *Entry = CostTableLookup(CostTblNoPairwise, ISD, MTy))
+ return LT.first * Entry->Cost;
+
+ return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwiseForm);
+}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 08c693ff38a..e71eb515cc2 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -166,6 +166,9 @@ public:
bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
TTI::ReductionFlags Flags) const;
+
+ int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
+ bool IsPairwiseForm);
/// @}
};
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