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-rw-r--r--llvm/lib/MC/ELFObjectWriter.cpp6
-rw-r--r--llvm/lib/MC/MCCodeView.cpp2
-rw-r--r--llvm/lib/MC/MCDwarf.cpp12
-rw-r--r--llvm/lib/Object/ArchiveWriter.cpp6
-rw-r--r--llvm/lib/ProfileData/InstrProfWriter.cpp11
-rw-r--r--llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp4
-rw-r--r--llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp45
-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp2
-rw-r--r--llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp15
-rw-r--r--llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp8
-rw-r--r--llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp11
-rw-r--r--llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp4
13 files changed, 50 insertions, 78 deletions
diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp
index 2255d059459..07b1d924e2b 100644
--- a/llvm/lib/MC/ELFObjectWriter.cpp
+++ b/llvm/lib/MC/ELFObjectWriter.cpp
@@ -183,10 +183,8 @@ public:
}
template <typename T> void write(T Val) {
- if (IsLittleEndian)
- support::endian::Writer<support::little>(getStream()).write(Val);
- else
- support::endian::Writer<support::big>(getStream()).write(Val);
+ support::endian::write(getStream(), Val,
+ IsLittleEndian ? support::little : support::big);
}
void writeHeader(const MCAssembler &Asm);
diff --git a/llvm/lib/MC/MCCodeView.cpp b/llvm/lib/MC/MCCodeView.cpp
index 7d79fc74c18..155fd7eeb57 100644
--- a/llvm/lib/MC/MCCodeView.cpp
+++ b/llvm/lib/MC/MCCodeView.cpp
@@ -632,7 +632,7 @@ void CodeViewContext::encodeDefRange(MCAsmLayout &Layout,
}
unsigned NumGaps = J - I - 1;
- support::endian::Writer<support::little> LEWriter(OS);
+ support::endian::Writer LEWriter(OS, support::little);
unsigned Bias = 0;
// We must split the range into chunks of MaxDefRange, this is a fundamental
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index 0e0ea965d14..57823e419f7 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -1798,6 +1798,8 @@ void MCDwarfFrameEmitter::EncodeAdvanceLoc(MCContext &Context,
// Scale the address delta by the minimum instruction length.
AddrDelta = ScaleAddrDelta(Context, AddrDelta);
+ support::endianness E =
+ Context.getAsmInfo()->isLittleEndian() ? support::little : support::big;
if (AddrDelta == 0) {
} else if (isUIntN(6, AddrDelta)) {
uint8_t Opcode = dwarf::DW_CFA_advance_loc | AddrDelta;
@@ -1807,16 +1809,10 @@ void MCDwarfFrameEmitter::EncodeAdvanceLoc(MCContext &Context,
OS << uint8_t(AddrDelta);
} else if (isUInt<16>(AddrDelta)) {
OS << uint8_t(dwarf::DW_CFA_advance_loc2);
- if (Context.getAsmInfo()->isLittleEndian())
- support::endian::Writer<support::little>(OS).write<uint16_t>(AddrDelta);
- else
- support::endian::Writer<support::big>(OS).write<uint16_t>(AddrDelta);
+ support::endian::write<uint16_t>(OS, AddrDelta, E);
} else {
assert(isUInt<32>(AddrDelta));
OS << uint8_t(dwarf::DW_CFA_advance_loc4);
- if (Context.getAsmInfo()->isLittleEndian())
- support::endian::Writer<support::little>(OS).write<uint32_t>(AddrDelta);
- else
- support::endian::Writer<support::big>(OS).write<uint32_t>(AddrDelta);
+ support::endian::write<uint32_t>(OS, AddrDelta, E);
}
}
diff --git a/llvm/lib/Object/ArchiveWriter.cpp b/llvm/lib/Object/ArchiveWriter.cpp
index 1a0137eb26e..c9796736896 100644
--- a/llvm/lib/Object/ArchiveWriter.cpp
+++ b/llvm/lib/Object/ArchiveWriter.cpp
@@ -136,10 +136,8 @@ static bool isBSDLike(object::Archive::Kind Kind) {
template <class T>
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val) {
- if (isBSDLike(Kind))
- support::endian::Writer<support::little>(Out).write(Val);
- else
- support::endian::Writer<support::big>(Out).write(Val);
+ support::endian::write(Out, Val,
+ isBSDLike(Kind) ? support::little : support::big);
}
static void printRestOfMemberHeader(
diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp
index 33ceb66fd26..18b9deec158 100644
--- a/llvm/lib/ProfileData/InstrProfWriter.cpp
+++ b/llvm/lib/ProfileData/InstrProfWriter.cpp
@@ -48,9 +48,10 @@ namespace llvm {
// back patching.
class ProfOStream {
public:
- ProfOStream(raw_fd_ostream &FD) : IsFDOStream(true), OS(FD), LE(FD) {}
+ ProfOStream(raw_fd_ostream &FD)
+ : IsFDOStream(true), OS(FD), LE(FD, support::little) {}
ProfOStream(raw_string_ostream &STR)
- : IsFDOStream(false), OS(STR), LE(STR) {}
+ : IsFDOStream(false), OS(STR), LE(STR, support::little) {}
uint64_t tell() { return OS.tell(); }
void write(uint64_t V) { LE.write<uint64_t>(V); }
@@ -85,7 +86,7 @@ public:
// true. Otherwise, \c OS will be an raw_string_ostream.
bool IsFDOStream;
raw_ostream &OS;
- support::endian::Writer<support::little> LE;
+ support::endian::Writer LE;
};
class InstrProfRecordWriterTrait {
@@ -112,7 +113,7 @@ public:
EmitKeyDataLength(raw_ostream &Out, key_type_ref K, data_type_ref V) {
using namespace support;
- endian::Writer<little> LE(Out);
+ endian::Writer LE(Out, little);
offset_type N = K.size();
LE.write<offset_type>(N);
@@ -139,7 +140,7 @@ public:
void EmitData(raw_ostream &Out, key_type_ref, data_type_ref V, offset_type) {
using namespace support;
- endian::Writer<little> LE(Out);
+ endian::Writer LE(Out, little);
for (const auto &ProfileData : *V) {
const InstrProfRecord &ProfRecord = ProfileData.second;
SummaryBuilder->addRecord(ProfRecord);
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index 25deddd5976..74e98dfd183 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -572,7 +572,7 @@ void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
- support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
+ support::endian::write<uint32_t>(OS, Binary, support::little);
++MCNumEmitted; // Keep track of the # of mi's emitted.
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index 0d471b1f5ce..3968a294cb1 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -148,11 +148,11 @@ void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
- support::endian::Writer<support::little>(OS).write(Value);
+ support::endian::write(OS, Value, support::little);
}
void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
- support::endian::Writer<support::little>(OS).write(Value);
+ support::endian::write(OS, Value, support::little);
}
unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
index b4ecfdee7bf..437f658caf6 100644
--- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
+++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
@@ -122,44 +122,35 @@ void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
computeAvailableFeatures(STI.getFeatureBits()));
unsigned Opcode = MI.getOpcode();
- support::endian::Writer<support::little> LE(OS);
- support::endian::Writer<support::big> BE(OS);
+ support::endian::Writer OSE(OS,
+ IsLittleEndian ? support::little : support::big);
if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
- LE.write<uint8_t>(Value >> 56);
+ OS << char(Value >> 56);
if (IsLittleEndian)
- LE.write<uint8_t>((Value >> 48) & 0xff);
+ OS << char((Value >> 48) & 0xff);
else
- LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff));
- LE.write<uint16_t>(0);
- if (IsLittleEndian)
- LE.write<uint32_t>(Value & 0xffffFFFF);
- else
- BE.write<uint32_t>(Value & 0xffffFFFF);
+ OS << char(SwapBits((Value >> 48) & 0xff));
+ OSE.write<uint16_t>(0);
+ OSE.write<uint32_t>(Value & 0xffffFFFF);
const MCOperand &MO = MI.getOperand(1);
uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
- LE.write<uint8_t>(0);
- LE.write<uint8_t>(0);
- LE.write<uint16_t>(0);
- if (IsLittleEndian)
- LE.write<uint32_t>(Imm >> 32);
- else
- BE.write<uint32_t>(Imm >> 32);
+ OSE.write<uint8_t>(0);
+ OSE.write<uint8_t>(0);
+ OSE.write<uint16_t>(0);
+ OSE.write<uint32_t>(Imm >> 32);
} else {
// Get instruction encoding and emit it
uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
- LE.write<uint8_t>(Value >> 56);
- if (IsLittleEndian) {
- LE.write<uint8_t>((Value >> 48) & 0xff);
- LE.write<uint16_t>((Value >> 32) & 0xffff);
- LE.write<uint32_t>(Value & 0xffffFFFF);
- } else {
- LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff));
- BE.write<uint16_t>((Value >> 32) & 0xffff);
- BE.write<uint32_t>(Value & 0xffffFFFF);
- }
+ OS << char(Value >> 56);
+ if (IsLittleEndian)
+ OS << char((Value >> 48) & 0xff);
+ else
+ OS << char(SwapBits((Value >> 48) & 0xff));
+ OSE.write<uint16_t>((Value >> 32) & 0xffff);
+ OSE.write<uint32_t>(Value & 0xffffFFFF);
}
}
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index b929b00e34a..3382684803a 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -452,7 +452,7 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI,
Binary |= SubBits0 | (SubBits1 << 16);
}
- support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
+ support::endian::write<uint32_t>(OS, Binary, support::little);
++MCNumEmitted;
}
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 92c8c224b71..2b948ca6002 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -122,25 +122,18 @@ public:
// Output the constant in big/little endian byte order.
unsigned Size = Desc.getSize();
+ support::endianness E = IsLittleEndian ? support::little : support::big;
switch (Size) {
case 0:
break;
case 4:
- if (IsLittleEndian) {
- support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
- } else {
- support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
- }
+ support::endian::write<uint32_t>(OS, Bits, E);
break;
case 8:
// If we emit a pair of instructions, the first one is
// always in the top 32 bits, even on little-endian.
- if (IsLittleEndian) {
- uint64_t Swapped = (Bits << 32) | (Bits >> 32);
- support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped);
- } else {
- support::endian::Writer<support::big>(OS).write<uint64_t>(Bits);
- }
+ support::endian::write<uint32_t>(OS, Bits >> 32, E);
+ support::endian::write<uint32_t>(OS, Bits, E);
break;
default:
llvm_unreachable("Invalid instruction size");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index b10cf79dc67..ad0e27d5c24 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -113,12 +113,12 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
.addReg(Ra)
.addOperand(MCOperand::createExpr(CallExpr));
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::Writer<support::little>(OS).write(Binary);
+ support::endian::write(OS, Binary, support::little);
// Emit JALR Ra, Ra, 0
TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::Writer<support::little>(OS).write(Binary);
+ support::endian::write(OS, Binary, support::little);
}
void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
@@ -140,12 +140,12 @@ void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
llvm_unreachable("Unhandled encodeInstruction length!");
case 2: {
uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
- support::endian::Writer<support::little>(OS).write<uint16_t>(Bits);
+ support::endian::write<uint16_t>(OS, Bits, support::little);
break;
}
case 4: {
uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
- support::endian::Writer<support::little>(OS).write(Bits);
+ support::endian::write(OS, Bits, support::little);
break;
}
}
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
index 684f66970db..647be159a15 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
@@ -98,14 +98,9 @@ void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
computeAvailableFeatures(STI.getFeatureBits()));
unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
-
- if (Ctx.getAsmInfo()->isLittleEndian()) {
- // Output the bits in little-endian byte order.
- support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
- } else {
- // Output the bits in big-endian byte order.
- support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
- }
+ support::endian::write(OS, Bits,
+ Ctx.getAsmInfo()->isLittleEndian() ? support::little
+ : support::big);
unsigned tlsOpNo = 0;
switch (MI.getOpcode()) {
default: break;
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
index d58c83d14ae..94ca94e1e18 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
@@ -118,11 +118,11 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
// TODO: MC converts all floating point immediate operands to double.
// This is fine for numeric values, but may cause NaNs to change bits.
float f = float(MO.getFPImm());
- support::endian::Writer<support::little>(OS).write<float>(f);
+ support::endian::write<float>(OS, f, support::little);
} else {
assert(Info.OperandType == WebAssembly::OPERAND_F64IMM);
double d = MO.getFPImm();
- support::endian::Writer<support::little>(OS).write<double>(d);
+ support::endian::write<double>(OS, d, support::little);
}
} else if (MO.isExpr()) {
const MCOperandInfo &Info = Desc.OpInfo[i];
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