diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 13 |
3 files changed, 43 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b79ad210389..d407774574b 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -2378,6 +2378,19 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, case Mips::Usw: return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::NORImm: + case Mips::NORImm64: + return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SLTImm64: + if (isInt<16>(Inst.getOperand(2).getImm())) { + Inst.setOpcode(Mips::SLTi64); + return MER_NotAMacro; + } + return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SLTUImm64: + if (isInt<16>(Inst.getOperand(2).getImm())) { + Inst.setOpcode(Mips::SLTiu64); + return MER_NotAMacro; + } return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ADDi: case Mips::ADDi_MM: case Mips::ADDiu: case Mips::ADDiu_MM: @@ -3868,9 +3881,18 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, case Mips::ANDi64: FinalOpcode = Mips::AND64; break; + case Mips::NORImm64: + FinalOpcode = Mips::NOR64; + break; case Mips::ORi64: FinalOpcode = Mips::OR64; break; + case Mips::SLTImm64: + FinalOpcode = Mips::SLT64; + break; + case Mips::SLTUImm64: + FinalOpcode = Mips::SLTu64; + break; case Mips::XORi64: FinalOpcode = Mips::XOR64; break; diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index b8396c1f599..2868b3be82f 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -892,3 +892,17 @@ let AdditionalPredicates = [NotInMicroMips] in { imm64:$imm), 0>, ISA_MIPS3_NOT_32R6_64R6; } + +def NORImm64 : NORIMM_DESC_BASE<GPR64Opnd, imm64>, GPR_64; +def : MipsInstAlias<"nor\t$rs, $imm", (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, + imm64:$imm)>, GPR_64; +def SLTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), + (ins GPR64Opnd:$rt, imm64:$imm), + "slt\t$rs, $rt, $imm">, GPR_64; +def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, + imm64:$imm)>, GPR_64; +def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), + (ins GPR64Opnd:$rt, imm64:$imm), + "sltu\t$rs, $rt, $imm">, GPR_64; +def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, + imm64:$imm)>, GPR_64; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index eeddea1ef66..830a8852b56 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2406,9 +2406,9 @@ let AdditionalPredicates = [NotInMicroMips] in { defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, GPR_32; - defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>; + defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, GPR_32; - defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>; + defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, GPR_32; } def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; @@ -2516,11 +2516,12 @@ def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), "jal\t$rs"> ; -def NORImm : MipsAsmPseudoInst< - (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), - "nor\t$rs, $rt, $imm">; +class NORIMM_DESC_BASE<RegisterOperand RO, DAGOperand Imm> : + MipsAsmPseudoInst<(outs RO:$rs), (ins RO:$rt, Imm:$imm), + "nor\t$rs, $rt, $imm">; +def NORImm : NORIMM_DESC_BASE<GPR32Opnd, simm32_relaxed>, GPR_32; def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, - simm32_relaxed:$imm)>; + simm32_relaxed:$imm)>, GPR_32; let hasDelaySlot = 1, isCTI = 1 in { def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), |
