diff options
Diffstat (limited to 'llvm/lib')
24 files changed, 97 insertions, 94 deletions
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp index f1290cb17e0..cbb96d8b05b 100644 --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -627,7 +627,7 @@ public: } }; -bool LanaiAsmParser::ParseDirective(AsmToken DirectiveId) { return true; } +bool LanaiAsmParser::ParseDirective(AsmToken /*DirectiveId*/) { return true; } bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, OperandVector &Operands, @@ -640,6 +640,7 @@ bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { case Match_Success: Out.EmitInstruction(Inst, SubtargetInfo); + Opcode = Inst.getOpcode(); return false; case Match_MissingFeature: return Error(IdLoc, "Instruction use requires option to be enabled"); @@ -688,10 +689,13 @@ std::unique_ptr<LanaiOperand> LanaiAsmParser::parseRegister() { bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) { + const AsmToken &Tok = getParser().getTok(); + StartLoc = Tok.getLoc(); + EndLoc = Tok.getEndLoc(); std::unique_ptr<LanaiOperand> Op = parseRegister(); - if (Op != 0) + if (Op != nullptr) RegNum = Op->getReg(); - return (Op == 0); + return (Op == nullptr); } std::unique_ptr<LanaiOperand> LanaiAsmParser::parseIdentifier() { @@ -1133,7 +1137,7 @@ static bool MaybePredicatedInst(const OperandVector &Operands) { .Default(false); } -bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo &Info, +bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo & /*Info*/, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { // First operand is token for instruction diff --git a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp index d8ead5d67bc..744441bc90d 100644 --- a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp +++ b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp @@ -30,7 +30,7 @@ namespace llvm { extern Target TheLanaiTarget; } -static MCDisassembler *createLanaiDisassembler(const Target &T, +static MCDisassembler *createLanaiDisassembler(const Target & /*T*/, const MCSubtargetInfo &STI, MCContext &Ctx) { return new LanaiDisassembler(STI, Ctx); @@ -71,8 +71,8 @@ static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, #include "LanaiGenDisassemblerTables.inc" -static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, - uint64_t &Size, uint32_t &Insn) { +static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t &Size, + uint32_t &Insn) { // We want to read exactly 4 bytes of data. if (Bytes.size() < 4) { Size = 0; @@ -127,14 +127,12 @@ static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { } } -DecodeStatus LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, - ArrayRef<uint8_t> Bytes, - uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const { +DecodeStatus LanaiDisassembler::getInstruction( + MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream & /*VStream*/, raw_ostream & /*CStream*/) const { uint32_t Insn; - DecodeStatus Result = readInstruction32(Bytes, Address, Size, Insn); + DecodeStatus Result = readInstruction32(Bytes, Size, Insn); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; @@ -161,7 +159,8 @@ static const unsigned GPRDecoderTable[] = { Lanai::R30, Lanai::R31}; DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t /*Address*/, + const void * /*Decoder*/) { if (RegNo > 31) return MCDisassembler::Fail; diff --git a/llvm/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp b/llvm/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp index 82b720cea8d..2fa411fcfd8 100644 --- a/llvm/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp +++ b/llvm/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp @@ -137,7 +137,7 @@ bool LanaiInstPrinter::printAlias(const MCInst *MI, raw_ostream &OS) { void LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, StringRef Annotation, - const MCSubtargetInfo &STI) { + const MCSubtargetInfo & /*STI*/) { if (!printAlias(MI, OS) && !printAliasInstr(MI, OS)) printInstruction(MI, OS); printAnnotation(OS, Annotation); @@ -233,7 +233,7 @@ static void printMemoryImmediateOffset(const MCAsmInfo &MAI, void LanaiInstPrinter::printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &OS, - const char *Modifier) { + const char * /*Modifier*/) { const MCOperand &RegOp = MI->getOperand(OpNo); const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); const MCOperand &AluOp = MI->getOperand(OpNo + 2); @@ -248,7 +248,7 @@ void LanaiInstPrinter::printMemRiOperand(const MCInst *MI, int OpNo, void LanaiInstPrinter::printMemRrOperand(const MCInst *MI, int OpNo, raw_ostream &OS, - const char *Modifier) { + const char * /*Modifier*/) { const MCOperand &RegOp = MI->getOperand(OpNo); const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); const MCOperand &AluOp = MI->getOperand(OpNo + 2); @@ -269,7 +269,7 @@ void LanaiInstPrinter::printMemRrOperand(const MCInst *MI, int OpNo, void LanaiInstPrinter::printMemSplsOperand(const MCInst *MI, int OpNo, raw_ostream &OS, - const char *Modifier) { + const char * /*Modifier*/) { const MCOperand &RegOp = MI->getOperand(OpNo); const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); const MCOperand &AluOp = MI->getOperand(OpNo + 2); diff --git a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp index d3ff9e8668d..9d39cef9f8e 100644 --- a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp +++ b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp @@ -47,8 +47,7 @@ public: const char *getPassName() const override { return "Lanai Assembly Printer"; } - void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, - const char *Modifier = 0); + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override; @@ -63,7 +62,7 @@ private: } // end of anonymous namespace void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - raw_ostream &O, const char *Modifier) { + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); switch (MO.getType()) { @@ -110,7 +109,7 @@ void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, // PrintAsmOperand - Print out an operand for an inline asm expression. bool LanaiAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, + unsigned /*AsmVariant*/, const char *ExtraCode, raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { diff --git a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp index 90157ead965..7b106547d60 100644 --- a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -83,7 +83,7 @@ char Filler::ID = 0; // createLanaiDelaySlotFillerPass - Returns a pass that fills in delay // slots in Lanai MachineFunctions FunctionPass * -llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine &tm) { +llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine & /*tm*/) { return new Filler(); } diff --git a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp index 1d32520daba..cb048d568df 100644 --- a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp @@ -140,7 +140,7 @@ void LanaiFrameLowering::emitPrologue(MachineFunction &MF, } MachineBasicBlock::iterator LanaiFrameLowering::eliminateCallFramePseudoInstr( - MachineFunction &MF, MachineBasicBlock &MBB, + MachineFunction & /*MF*/, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { // Discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. return MBB.erase(I); @@ -176,7 +176,7 @@ MachineBasicBlock::iterator LanaiFrameLowering::eliminateCallFramePseudoInstr( // ld -8[%fp],%fp # restore the caller's frame pointer // before RET and the delay slot filler will move RET such that these // instructions execute in the delay slots of the load to PC. -void LanaiFrameLowering::emitEpilogue(MachineFunction &MF, +void LanaiFrameLowering::emitEpilogue(MachineFunction & /*MF*/, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const LanaiInstrInfo &LII = diff --git a/llvm/lib/Target/Lanai/LanaiFrameLowering.h b/llvm/lib/Target/Lanai/LanaiFrameLowering.h index 808a96638c0..2f9b6c3c158 100644 --- a/llvm/lib/Target/Lanai/LanaiFrameLowering.h +++ b/llvm/lib/Target/Lanai/LanaiFrameLowering.h @@ -46,7 +46,7 @@ public: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override; - bool hasFP(const MachineFunction &MF) const override { return true; } + bool hasFP(const MachineFunction & /*MF*/) const override { return true; } void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp index 24172736d48..29bc6e8a6c5 100644 --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -201,7 +201,7 @@ bool LanaiDAGToDAGISel::selectAddrRiSpls(SDValue Addr, SDValue &Base, bool LanaiDAGToDAGISel::selectAddrRi(SDValue Addr, SDValue &Base, SDValue &Offset, SDValue &AluOp) { - return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RImode=*/true); + return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/true); } bool LanaiDAGToDAGISel::selectAddrSpls(SDValue Addr, SDValue &Base, diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index b18348d4fed..66416b38e81 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -197,8 +197,8 @@ SDValue LanaiTargetLowering::LowerOperation(SDValue Op, // Lanai Inline Assembly Support //===----------------------------------------------------------------------===// -unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT VT, - SelectionDAG &DAG) const { +unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/, + SelectionDAG & /*DAG*/) const { // Only unallocatable registers should be matched here. unsigned Reg = StringSwitch<unsigned>(RegName) .Case("pc", Lanai::PC) @@ -579,7 +579,7 @@ LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. SDValue LanaiTargetLowering::LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg, - bool IsTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, + bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { @@ -626,7 +626,7 @@ SDValue LanaiTargetLowering::LowerCCCCallTo( Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align, /*IsVolatile=*/false, /*AlwaysInline=*/false, - /*IsTailCall=*/false, MachinePointerInfo(), + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); ByValArgs.push_back(FIPtr); } @@ -786,8 +786,7 @@ SDValue LanaiTargetLowering::LowerCallResult( //===----------------------------------------------------------------------===// static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, - SDValue &LHS, SDValue &RHS, - SelectionDAG &DAG) { + SDValue &RHS, SelectionDAG &DAG) { ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT, @@ -859,7 +858,7 @@ SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { SDValue Dest = Op.getOperand(4); SDLoc DL(Op); - LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG); + LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG); SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); SDValue Flag = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC); @@ -961,7 +960,7 @@ SDValue LanaiTargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const { SDValue Cond = Op.getOperand(3); SDLoc DL(Op); - LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG); + LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG); SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry); return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); @@ -973,7 +972,7 @@ SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { SDValue Cond = Op.getOperand(2); SDLoc DL(Op); - LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG); + LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG); SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); SDValue Flag = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC); @@ -990,7 +989,7 @@ SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op, SDValue Cond = Op.getOperand(4); SDLoc DL(Op); - LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG); + LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG); SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32); SDValue Flag = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC); diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index e2a57a1caba..673d23daf88 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -51,7 +51,7 @@ void LanaiInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo *RegisterInfo) const { + const TargetRegisterInfo * /*RegisterInfo*/) const { DebugLoc DL; if (Position != MBB.end()) { DL = Position->getDebugLoc(); @@ -71,7 +71,7 @@ void LanaiInstrInfo::loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo *RegisterInfo) const { + const TargetRegisterInfo * /*RegisterInfo*/) const { DebugLoc DL; if (Position != MBB.end()) { DL = Position->getDebugLoc(); @@ -86,9 +86,8 @@ void LanaiInstrInfo::loadRegFromStackSlot( .addImm(LPAC::ADD); } -bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, - MachineInstr &MIb, - AliasAnalysis *AA) const { +bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint( + MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis * /*AA*/) const { assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); @@ -118,7 +117,7 @@ bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, return false; } -bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { +bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr & /*MI*/) const { return false; } @@ -283,7 +282,7 @@ inline static unsigned flagSettingOpcodeVariant(unsigned OldOpcode) { } bool LanaiInstrInfo::optimizeCompareInstr( - MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, + MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, int CmpValue, const MachineRegisterInfo *MRI) const { // Get the unique definition of SrcReg. MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); @@ -457,8 +456,7 @@ bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI, // Identify instructions that can be folded into a SELECT instruction, and // return the defining instruction. static MachineInstr *canFoldIntoSelect(unsigned Reg, - const MachineRegisterInfo &MRI, - const TargetInstrInfo *TII) { + const MachineRegisterInfo &MRI) { if (!TargetRegisterInfo::isVirtualRegister(Reg)) return nullptr; if (!MRI.hasOneNonDBGUse(Reg)) @@ -495,13 +493,13 @@ static MachineInstr *canFoldIntoSelect(unsigned Reg, MachineInstr * LanaiInstrInfo::optimizeSelect(MachineInstr &MI, SmallPtrSetImpl<MachineInstr *> &SeenMIs, - bool PreferFalse) const { + bool /*PreferFalse*/) const { assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction"); MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); - MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI, this); + MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); bool Invert = !DefMI; if (!DefMI) - DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI, this); + DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); if (!DefMI) return nullptr; @@ -552,7 +550,7 @@ LanaiInstrInfo::optimizeSelect(MachineInstr &MI, return NewMI; } -// The AnalyzeBranch function is used to examine conditional instructions and +// The analyzeBranch function is used to examine conditional instructions and // remove unnecessary instructions. This method is used by BranchFolder and // IfConverter machine function passes to improve the CFG. // - TrueBlock is set to the destination if condition evaluates true (it is the @@ -749,7 +747,7 @@ unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI, bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth( MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo * /*TRI*/) const { // Handle only loads/stores with base register followed by immediate offset // and with add as ALU op. if (LdSt.getNumOperands() != 4) diff --git a/llvm/lib/Target/Lanai/LanaiMCInstLower.h b/llvm/lib/Target/Lanai/LanaiMCInstLower.h index 9ea8a36c1ef..41c0766e86d 100644 --- a/llvm/lib/Target/Lanai/LanaiMCInstLower.h +++ b/llvm/lib/Target/Lanai/LanaiMCInstLower.h @@ -31,7 +31,7 @@ class LLVM_LIBRARY_VISIBILITY LanaiMCInstLower { AsmPrinter &Printer; public: - LanaiMCInstLower(MCContext &CTX, Mangler &Mang, AsmPrinter &AP) + LanaiMCInstLower(MCContext &CTX, Mangler & /*Mang*/, AsmPrinter &AP) : Ctx(CTX), Printer(AP) {} void Lower(const MachineInstr *MI, MCInst &OutMI) const; diff --git a/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp b/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp index 7bfe992d1d5..a4c612258e7 100644 --- a/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp @@ -34,7 +34,7 @@ using namespace llvm; LanaiRegisterInfo::LanaiRegisterInfo() : LanaiGenRegisterInfo(Lanai::RCA) {} const uint16_t * -LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { +LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction * /*MF*/) const { return CSR_SaveList; } @@ -61,12 +61,12 @@ BitVector LanaiRegisterInfo::getReservedRegs(const MachineFunction &MF) const { } bool LanaiRegisterInfo::requiresRegisterScavenging( - const MachineFunction &MF) const { + const MachineFunction & /*MF*/) const { return true; } bool LanaiRegisterInfo::trackLivenessAfterRegAlloc( - const MachineFunction &MF) const { + const MachineFunction & /*MF*/) const { return true; } @@ -257,7 +257,8 @@ bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const { unsigned LanaiRegisterInfo::getRARegister() const { return Lanai::RCA; } -unsigned LanaiRegisterInfo::getFrameRegister(const MachineFunction &MF) const { +unsigned +LanaiRegisterInfo::getFrameRegister(const MachineFunction & /*MF*/) const { return Lanai::FP; } @@ -280,7 +281,7 @@ unsigned LanaiRegisterInfo::getEHHandlerRegister() const { } const uint32_t * -LanaiRegisterInfo::getCallPreservedMask(const MachineFunction &MF, - CallingConv::ID CC) const { +LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/, + CallingConv::ID /*CC*/) const { return CSR_RegMask; } diff --git a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp index 82a767612e2..b71c30fe3e0 100644 --- a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp @@ -20,9 +20,11 @@ namespace llvm { SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy( - SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, - MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { + SelectionDAG & /*DAG*/, const SDLoc & /*dl*/, SDValue /*Chain*/, + SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, unsigned /*Align*/, + bool /*isVolatile*/, bool /*AlwaysInline*/, + MachinePointerInfo /*DstPtrInfo*/, + MachinePointerInfo /*SrcPtrInfo*/) const { ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); if (!ConstantSize) return SDValue(); diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp index bfe07170050..0fa5e82a7a6 100644 --- a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp +++ b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp @@ -39,9 +39,9 @@ LanaiSubtarget &LanaiSubtarget::initializeSubtargetDependencies(StringRef CPU, LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu, StringRef FeatureString, const TargetMachine &TM, - const TargetOptions &Options, - CodeModel::Model CodeModel, - CodeGenOpt::Level OptLevel) + const TargetOptions & /*Options*/, + CodeModel::Model /*CodeModel*/, + CodeGenOpt::Level /*OptLevel*/) : LanaiGenSubtargetInfo(TargetTriple, Cpu, FeatureString), FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)), InstrInfo(), TLInfo(TM, *this), TSInfo() {} diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index 2d1846c9874..b1f4b496eb9 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -35,7 +35,7 @@ extern "C" void LLVMInitializeLanaiTarget() { RegisterTargetMachine<LanaiTargetMachine> registered_target(TheLanaiTarget); } -static std::string computeDataLayout(const Triple &TT) { +static std::string computeDataLayout() { // Data layout (keep in sync with clang/lib/Basic/Targets.cpp) return "E" // Big endian "-m:e" // ELF name manging @@ -46,8 +46,7 @@ static std::string computeDataLayout(const Triple &TT) { "-S64"; // 64 bit natural stack alignment } -static Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional<Reloc::Model> RM) { +static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { if (!RM.hasValue()) return Reloc::PIC_; return *RM; @@ -59,9 +58,8 @@ LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT, Optional<Reloc::Model> RM, CodeModel::Model CodeModel, CodeGenOpt::Level OptLevel) - : LLVMTargetMachine(T, computeDataLayout(TargetTriple), TT, Cpu, - FeatureString, Options, getEffectiveRelocModel(TT, RM), - CodeModel, OptLevel), + : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, + getEffectiveRelocModel(RM), CodeModel, OptLevel), Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel), TLOF(new LanaiTargetObjectFile()) { initAsmInfo(); diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h index 1f616085cdb..5278c70d909 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -37,7 +37,7 @@ public: CodeModel::Model CodeModel, CodeGenOpt::Level OptLevel); const LanaiSubtarget * - getSubtargetImpl(const llvm::Function &Fn) const override { + getSubtargetImpl(const llvm::Function & /*Fn*/) const override { return &Subtarget; } diff --git a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp index 65764d09482..4048c853521 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp @@ -72,7 +72,7 @@ bool LanaiTargetObjectFile::isGlobalInSmallSection(const GlobalValue *GV, // section. This method does all the work, except for checking the section // kind. bool LanaiTargetObjectFile::isGlobalInSmallSectionImpl( - const GlobalValue *GV, const TargetMachine &TM) const { + const GlobalValue *GV, const TargetMachine & /*TM*/) const { // Only global variables, not functions. const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV); if (!GVA) diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h index 755f0aa1663..6300d2502d6 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h +++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h @@ -44,8 +44,7 @@ public: LanaiTTIImpl(const LanaiTTIImpl &Arg) : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} LanaiTTIImpl(LanaiTTIImpl &&Arg) - : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), - TLI(std::move(Arg.TLI)) {} + : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(Arg.ST), TLI(Arg.TLI) {} bool shouldBuildLookupTables() const { return false; } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp index daf542f41cd..a3d8699f131 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp @@ -55,9 +55,9 @@ public: MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override; // No instruction requires relaxation - bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, - const MCRelaxableFragment *DF, - const MCAsmLayout &Layout) const override { + bool fixupNeedsRelaxation(const MCFixup & /*Fixup*/, uint64_t /*Value*/, + const MCRelaxableFragment * /*DF*/, + const MCAsmLayout & /*Layout*/) const override { return false; } @@ -67,10 +67,13 @@ public: return Lanai::NumTargetFixupKinds; } - bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } + bool mayNeedRelaxation(const MCInst & /*Inst*/) const override { + return false; + } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} + void relaxInstruction(const MCInst & /*Inst*/, + const MCSubtargetInfo & /*STI*/, + MCInst & /*Res*/) const override {} bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; }; @@ -86,8 +89,8 @@ bool LanaiAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { } void LanaiAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, - unsigned DataSize, uint64_t Value, - bool IsPCRel) const { + unsigned /*DataSize*/, uint64_t Value, + bool /*IsPCRel*/) const { MCFixupKind Kind = Fixup.getKind(); Value = adjustFixupValue(static_cast<unsigned>(Kind), Value); @@ -159,9 +162,9 @@ LanaiAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { } // namespace MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T, - const MCRegisterInfo &MRI, + const MCRegisterInfo & /*MRI*/, const Triple &TheTriple, - StringRef CPU) { + StringRef /*CPU*/) { if (!TheTriple.isOSBinFormatELF()) llvm_unreachable("OS not supported"); diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp index d11eb0ab81d..e30d5e9a18e 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp @@ -33,15 +33,15 @@ protected: } // namespace LanaiELFObjectWriter::LanaiELFObjectWriter(uint8_t OSABI) - : MCELFObjectTargetWriter(/*Is64Bit=*/false, OSABI, ELF::EM_LANAI, + : MCELFObjectTargetWriter(/*Is64Bit_=*/false, OSABI, ELF::EM_LANAI, /*HasRelocationAddend=*/true) {} LanaiELFObjectWriter::~LanaiELFObjectWriter() {} -unsigned LanaiELFObjectWriter::getRelocType(MCContext &Ctx, - const MCValue &Target, +unsigned LanaiELFObjectWriter::getRelocType(MCContext & /*Ctx*/, + const MCValue & /*Target*/, const MCFixup &Fixup, - bool IsPCRel) const { + bool /*IsPCRel*/) const { unsigned Type; unsigned Kind = static_cast<unsigned>(Fixup.getKind()); switch (Kind) { @@ -74,7 +74,7 @@ unsigned LanaiELFObjectWriter::getRelocType(MCContext &Ctx, return Type; } -bool LanaiELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &SD, +bool LanaiELFObjectWriter::needsRelocateWithSymbol(const MCSymbol & /*SD*/, unsigned Type) const { switch (Type) { case ELF::R_LANAI_21: diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp index 491a7084757..7e2705e67b6 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp @@ -19,7 +19,7 @@ using namespace llvm; void LanaiMCAsmInfo::anchor() {} -LanaiMCAsmInfo::LanaiMCAsmInfo(const Triple &TheTriple) { +LanaiMCAsmInfo::LanaiMCAsmInfo(const Triple & /*TheTriple*/) { IsLittleEndian = false; PrivateGlobalPrefix = ".L"; WeakRefDirective = "\t.weak\t"; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp index b4ffa7c23bf..f14adc27dd4 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp @@ -320,6 +320,7 @@ unsigned LanaiMCCodeEmitter::getBranchTargetOpValue( llvm::MCCodeEmitter * llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo, - const MCRegisterInfo &MRI, MCContext &context) { + const MCRegisterInfo & /*MRI*/, + MCContext &context) { return new LanaiMCCodeEmitter(InstrInfo, context); } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h index f481b039bda..5004d541ff7 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h @@ -45,7 +45,7 @@ public: } // There are no TLS LanaiMCExprs at the moment. - void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {} + void fixELFSymbolsInTLSFixups(MCAssembler & /*Asm*/) const override {} static bool classof(const MCExpr *E) { return E->getKind() == MCExpr::Target; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp index 3bc2e8bc2c3..04bedfb7fba 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -39,7 +39,7 @@ static MCInstrInfo *createLanaiMCInstrInfo() { return X; } -static MCRegisterInfo *createLanaiMCRegisterInfo(const Triple &TT) { +static MCRegisterInfo *createLanaiMCRegisterInfo(const Triple & /*TT*/) { MCRegisterInfo *X = new MCRegisterInfo(); InitLanaiMCRegisterInfo(X, Lanai::RCA, 0, 0, Lanai::PC); return X; @@ -63,7 +63,7 @@ static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll); } -static MCInstPrinter *createLanaiMCInstPrinter(const Triple &T, +static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, |
