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-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrFormats.td39
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrInfo.td33
2 files changed, 27 insertions, 45 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index ad7c08be88d..c72879a1339 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -1684,14 +1684,11 @@ class StoreInherentS<string mnemonic, bits<16> opcode>
}
class SideEffectInherentE<string mnemonic, bits<16>opcode>
- : InstE<opcode, (outs), (ins), mnemonic, []> {
- let hasSideEffects = 1;
-}
+ : InstE<opcode, (outs), (ins), mnemonic, []>;
class SideEffectInherentS<string mnemonic, bits<16> opcode,
SDPatternOperator operator>
: InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
- let hasSideEffects = 1;
let BD2 = 0;
}
@@ -2260,23 +2257,18 @@ multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
: InstI<opcode, (outs), (ins imm:$I1),
- mnemonic#"\t$I1", []> {
- let hasSideEffects = 1;
-}
+ mnemonic#"\t$I1", []>;
class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
: InstRR<opcode, (outs), (ins cls:$R1),
mnemonic#"\t$R1", []> {
- let hasSideEffects = 1;
let R2 = 0;
}
class SideEffectUnaryS<string mnemonic, bits<16> opcode,
SDPatternOperator operator>
: InstS<opcode, (outs), (ins bdaddr12only:$BD2),
- mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
- let hasSideEffects = 1;
-}
+ mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]>;
class LoadAddressRX<string mnemonic, bits<8> opcode,
SDPatternOperator operator, AddressingMode mode>
@@ -2537,15 +2529,12 @@ class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
RegisterOperand cls>
: InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
- mnemonic##"\t$R1, $XBD2", []> {
- let hasSideEffects = 1;
-}
+ mnemonic##"\t$R1, $XBD2", []>;
class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
RegisterOperand cls>
: InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
mnemonic##"\t$R1, $RI2", []> {
- let hasSideEffects = 1;
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
// However, BDXs have two extra operands and are therefore 6 units more
// complex.
@@ -2555,16 +2544,12 @@ class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
Immediate imm1, Immediate imm2>
: InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
- mnemonic#"\t$I1, $I2", []> {
- let hasSideEffects = 1;
-}
+ mnemonic#"\t$I1, $I2", []>;
class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
SDPatternOperator operator, Immediate imm>
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
- mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]> {
- let hasSideEffects = 1;
-}
+ mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
@@ -3287,17 +3272,13 @@ class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
RegisterOperand cls1, RegisterOperand cls2,
Immediate imm>
: InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
- mnemonic#"\t$R1, $R2, $M3", []> {
- let hasSideEffects = 1;
-}
+ mnemonic#"\t$R1, $R2, $M3", []>;
class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
RegisterOperand cls>
: InstSSF<opcode, (outs),
(ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
- mnemonic#"\t$BD1, $BD2, $R3", []> {
- let hasSideEffects = 1;
-}
+ mnemonic#"\t$BD1, $BD2, $R3", []>;
class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2>
@@ -3716,9 +3697,7 @@ class Pseudo<dag outs, dag ins, list<dag> pattern>
// Like SideEffectBinarySIL, but expanded later.
class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
: Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
- [(operator bdaddr12only:$BD1, imm:$I2)]> {
- let hasSideEffects = 1;
-}
+ [(operator bdaddr12only:$BD1, imm:$I2)]>;
// Like UnaryRI, but expanded after RA depending on the choice of register.
class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index d97a92dd109..57a620bca78 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1584,7 +1584,7 @@ let Uses = [CC] in
def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>;
// Set CC and program mask from a register.
-let Defs = [CC] in
+let hasSideEffects = 1, Defs = [CC] in
def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>;
// Branch and link - like BAS, but also extracts CC and program mask.
@@ -1598,9 +1598,11 @@ let Defs = [CC] in
def TAM : SideEffectInherentE<"tam", 0x010B>;
// Set addressing mode.
-def SAM24 : SideEffectInherentE<"sam24", 0x010C>;
-def SAM31 : SideEffectInherentE<"sam31", 0x010D>;
-def SAM64 : SideEffectInherentE<"sam64", 0x010E>;
+let hasSideEffects = 1 in {
+ def SAM24 : SideEffectInherentE<"sam24", 0x010C>;
+ def SAM31 : SideEffectInherentE<"sam31", 0x010D>;
+ def SAM64 : SideEffectInherentE<"sam64", 0x010E>;
+}
// Branch and set mode. Not really a call, but also sets an output register.
let isBranch = 1, isTerminator = 1, isBarrier = 1 in
@@ -1614,7 +1616,7 @@ let isCall = 1, Defs = [CC] in
// Transactional execution
//===----------------------------------------------------------------------===//
-let Predicates = [FeatureTransactionalExecution] in {
+let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in {
// Transaction Begin
let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in {
def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>;
@@ -1633,12 +1635,10 @@ let Predicates = [FeatureTransactionalExecution] in {
def TABORT : SideEffectUnaryS<"tabort", 0xB2FC, int_s390_tabort>;
// Nontransactional Store
- let hasSideEffects = 1 in
- def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
+ def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
// Extract Transaction Nesting Depth
- let hasSideEffects = 1 in
- def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>;
+ def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>;
}
//===----------------------------------------------------------------------===//
@@ -1646,7 +1646,8 @@ let Predicates = [FeatureTransactionalExecution] in {
//===----------------------------------------------------------------------===//
let Predicates = [FeatureProcessorAssist] in {
- def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>;
+ let hasSideEffects = 1 in
+ def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>;
def : Pat<(int_s390_ppa_txassist GR32:$src),
(PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
0, 1)>;
@@ -1685,7 +1686,7 @@ let mayLoad = 1, Defs = [CC] in
defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
// Supervisor call.
-let isCall = 1, Defs = [CC] in
+let hasSideEffects = 1, isCall = 1, Defs = [CC] in
def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>;
// Store clock.
@@ -1700,15 +1701,17 @@ let hasSideEffects = 1, Defs = [CC] in
def STFLE : StoreInherentS<"stfle", 0xB2B0>;
// Extract CPU time.
-let Defs = [R0D, R1D], mayLoad = 1 in
+let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in
def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>;
// Execute.
-def EX : SideEffectBinaryRX<"ex", 0x44, GR64>;
-def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>;
+let hasSideEffects = 1 in {
+ def EX : SideEffectBinaryRX<"ex", 0x44, GR64>;
+ def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>;
+}
// Program return.
-let Defs = [CC] in
+let hasSideEffects = 1, Defs = [CC] in
def PR : SideEffectInherentE<"pr", 0x0101>;
// Move with key.
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