diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Support/Host.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedA53.td | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp index a70c0f7c11a..29ebad40256 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp @@ -1382,7 +1382,7 @@ DIE *DwarfUnit::getOrCreateSubprogramDIE(DISubprogram SP) { if (DISubprogram SPDecl = SP.getFunctionDeclaration()) { // Add subprogram definitions to the CU die directly. ContextDIE = &getUnitDie(); - // Build the decl now to ensure it preceeds the definition. + // Build the decl now to ensure it precedes the definition. getOrCreateSubprogramDIE(SPDecl); } diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index fd0472ee2f7..ce0a3b6bed7 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -744,7 +744,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) { .Default(""); #if defined(__aarch64__) - // We need to check crypto seperately since we need all of the crypto + // We need to check crypto separately since we need all of the crypto // extensions to enable the subtarget feature if (CPUFeatures[I] == "aes") crypto |= CAP_AES; diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td index 0c3949ecfc1..d709bee7b9e 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA53.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td @@ -148,9 +148,9 @@ def : ReadAdvance<ReadVLD, 0>; // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // operands are needed one cycle later if and only if they are to be -// shifted. Otherwise, they too are needed two cycle later. This same +// shifted. Otherwise, they too are needed two cycles later. This same // ReadAdvance applies to Extended registers as well, even though there is -// a seperate SchedPredicate for them. +// a separate SchedPredicate for them. def : ReadAdvance<ReadI, 2, [WriteImm,WriteI, WriteISReg, WriteIEReg,WriteIS, WriteID32,WriteID64, |
