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-rw-r--r--llvm/lib/Target/ARM/ARM.td4
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td3
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb.td19
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb2.td31
-rw-r--r--llvm/lib/Target/ARM/ARMInstrVFP.td31
-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.cpp1
-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.h4
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp2
8 files changed, 1 insertions, 94 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index dad42326676..e02815ea335 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -89,8 +89,6 @@ def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
"Enable support for Performance Monitor extensions">;
def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
"Enable support for TrustZone security extensions">;
-def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
- "Enable support for ARMv8-M Security Extensions">;
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable support for Cryptography extensions",
[FeatureNEON]>;
@@ -396,7 +394,6 @@ def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
FeatureDB,
FeatureHWDiv,
FeatureV7Clrex,
- Feature8MSecExt,
FeatureAcquireRelease,
FeatureMClass]>;
@@ -405,7 +402,6 @@ def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
FeatureNoARM,
FeatureDB,
FeatureHWDiv,
- Feature8MSecExt,
FeatureAcquireRelease,
FeatureMClass]>;
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index d21268ea39f..d068722f4ba 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -272,9 +272,6 @@ def HasVirtualization: Predicate<"false">,
def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
AssemblerPredicate<"FeatureTrustZone",
"TrustZone">;
-def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">,
- AssemblerPredicate<"Feature8MSecExt",
- "ARMv8-M Security Extensions">;
def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 842ddcde494..5b1f9a06442 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -439,14 +439,6 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
let Inst{2-0} = 0b000;
let Unpredictable{2-0} = 0b111;
}
- def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
- Requires<[IsThumb, Has8MSecExt]>,
- T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
- bits<4> Rm;
- let Inst{6-3} = Rm;
- let Inst{2-0} = 0b100;
- let Unpredictable{1-0} = 0b11;
- }
}
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
@@ -504,17 +496,6 @@ let isCall = 1,
let Inst{2-0} = 0b000;
}
- // ARMv8-M Security Extensions
- def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,
- "blxns${p}\t$func", []>,
- Requires<[IsThumb, Has8MSecExt]>,
- T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
- bits<4> func;
- let Inst{6-3} = func;
- let Inst{2-0} = 0b100;
- let Unpredictable{1-0} = 0b11;
- }
-
// ARMv4T
def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
4, IIC_Br,
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 7f0d16f7967..f0e5739dfd8 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -4336,37 +4336,6 @@ def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
}
//===----------------------------------------------------------------------===//
-// ARMv8-M Security Extensions instructions
-//
-
-let hasSideEffects = 1 in
-def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
- Requires<[Has8MSecExt]> {
- let Inst = 0xe97fe97f;
-}
-
-class T2TT<bits<2> at, string asm, list<dag> pattern>
- : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
- pattern> {
- bits<4> Rn;
- bits<4> Rt;
-
- let Inst{31-20} = 0b111010000100;
- let Inst{19-16} = Rn;
- let Inst{15-12} = 0b1111;
- let Inst{11-8} = Rt;
- let Inst{7-6} = at;
- let Inst{5-0} = 0b000000;
-
- let Unpredictable{5-0} = 0b111111;
-}
-
-def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
-
-//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index feeca0720d0..63e7940bb14 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -200,37 +200,6 @@ defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
def : MnemonicAlias<"vldm", "vldmia">;
def : MnemonicAlias<"vstm", "vstmia">;
-
-//===----------------------------------------------------------------------===//
-// Lazy load / store multiple Instructions
-//
-let mayLoad = 1 in
-def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
- IIC_fpLoad_m, "vlldm${p}\t$Rn", "", []>,
- Requires<[HasV8MMainline, Has8MSecExt]> {
- let Inst{24-23} = 0b00;
- let Inst{22} = 0;
- let Inst{21} = 1;
- let Inst{20} = 1;
- let Inst{15-12} = 0;
- let Inst{7-0} = 0;
- let mayLoad = 1;
-}
-
-let mayStore = 1 in
-def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
- IIC_fpStore_m, "vlstm${p}\t$Rn", "", []>,
- Requires<[HasV8MMainline, Has8MSecExt]> {
- let Inst{24-23} = 0b00;
- let Inst{22} = 0;
- let Inst{21} = 1;
- let Inst{20} = 0;
- let Inst{15-12} = 0;
- let Inst{7-0} = 0;
- let mayStore = 1;
-}
-
-
// FLDM/FSTM - Load / Store multiple single / double precision registers for
// pre-ARMv6 cores.
// These instructions are deprecated!
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index a7d59ecf1c1..0fdb1959b58 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -148,7 +148,6 @@ void ARMSubtarget::initializeEnvironment() {
FPOnlySP = false;
HasPerfMon = false;
HasTrustZone = false;
- Has8MSecExt = false;
HasCrypto = false;
HasCRC = false;
HasZeroCycleZeroing = false;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index efa3196503e..d5f0b59a54b 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -201,9 +201,6 @@ protected:
/// HasTrustZone - if true, processor supports TrustZone security extensions
bool HasTrustZone;
- /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
- bool Has8MSecExt;
-
/// HasCrypto - if true, processor supports Cryptography extensions
bool HasCrypto;
@@ -369,7 +366,6 @@ public:
bool isFPOnlySP() const { return FPOnlySP; }
bool hasPerfMon() const { return HasPerfMon; }
bool hasTrustZone() const { return HasTrustZone; }
- bool has8MSecExt() const { return Has8MSecExt; }
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
bool prefers32BitThumb() const { return Pref32BitThumb; }
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 277304d5634..5a63f04d6ab 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5268,7 +5268,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
- Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic.startswith("vsel"))
+ Mnemonic.startswith("vsel"))
return Mnemonic;
// First, split out any predication code. Ignore mnemonics we know aren't
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