diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleP5600.td | 6 |
3 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td index f21850c74ee..daca8b90708 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td @@ -515,6 +515,7 @@ class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> { + bit hasNoSchedulingInfo = 1; bit usesCustomInserter = 1; } diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index 1e9ce834057..907ed9ef746 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1239,6 +1239,7 @@ class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { bit usesCustomInserter = 1; + bit hasNoSchedulingInfo = 1; } class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, @@ -1446,6 +1447,7 @@ class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, ROIdx:$n))]> { bit usesCustomInserter = 1; + bit hasNoSchedulingInfo = 1; string Constraints = "$wd = $wd_in"; } @@ -2043,7 +2045,7 @@ class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, // 1.0 when we only need to match ISD::FEXP2. class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; -let usesCustomInserter = 1 in { +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { class FEXP2_W_1_PSEUDO_DESC : MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; @@ -3737,6 +3739,7 @@ class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, (ins RCWS:$ws), [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { bit usesCustomInserter = 1; + bit hasNoSchedulingInfo = 1; } def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, @@ -3773,7 +3776,7 @@ let ASEPredicate = [HasMSA] in { [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>; } - let usesCustomInserter = 1 in { + let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws), [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>; diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index f529fc41b45..239d18c3817 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -288,6 +288,8 @@ def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>; +def : InstRW<[P5600WriteMSAShortInt], + (instregex "^BSEL_(H|W|D|FW|FD)_PSEUDO$")>; // pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; @@ -335,6 +337,10 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>; def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; +def : InstRW<[P5600WriteMSAShortLogic], + (instregex "^(AND|OR|[XN]OR)_V_[DHW]_PSEUDO$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^FILL_F(D|W)_PSEUDO$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSERT_F(D|W)_PSEUDO$")>; // fexp2_w, fexp2_d def : InstRW<[P5600WriteFPUS], (instregex "^FEXP2_(W|D)$")>; |
