diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 49 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIIntrinsics.td | 18 |
2 files changed, 0 insertions, 67 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index ca9866f441c..a98183b28bb 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5818,55 +5818,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, } return SDValue(); }; - case SIIntrinsic::SI_tbuffer_store: { - - // Extract vindex and voffset from vaddr as appropriate - const ConstantSDNode *OffEn = cast<ConstantSDNode>(Op.getOperand(10)); - const ConstantSDNode *IdxEn = cast<ConstantSDNode>(Op.getOperand(11)); - SDValue VAddr = Op.getOperand(5); - - SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); - - assert(!(OffEn->isOne() && IdxEn->isOne()) && - "Legacy intrinsic doesn't support both offset and index - use new version"); - - SDValue VIndex = IdxEn->isOne() ? VAddr : Zero; - SDValue VOffset = OffEn->isOne() ? VAddr : Zero; - - // Deal with the vec-3 case - const ConstantSDNode *NumChannels = cast<ConstantSDNode>(Op.getOperand(4)); - auto Opcode = NumChannels->getZExtValue() == 3 ? - AMDGPUISD::TBUFFER_STORE_FORMAT_X3 : AMDGPUISD::TBUFFER_STORE_FORMAT; - - unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue(); - unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue(); - unsigned Glc = cast<ConstantSDNode>(Op.getOperand(12))->getZExtValue(); - unsigned Slc = cast<ConstantSDNode>(Op.getOperand(13))->getZExtValue(); - SDValue Ops[] = { - Chain, - Op.getOperand(3), // vdata - Op.getOperand(2), // rsrc - VIndex, - VOffset, - Op.getOperand(6), // soffset - Op.getOperand(7), // inst_offset - DAG.getConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format - DAG.getConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy - DAG.getConstant(IdxEn->isOne(), DL, MVT::i1), // idxen - }; - - assert((cast<ConstantSDNode>(Op.getOperand(14)))->getZExtValue() == 0 && - "Value of tfe other than zero is unsupported"); - - EVT VT = Op.getOperand(3).getValueType(); - MachineMemOperand *MMO = MF.getMachineMemOperand( - MachinePointerInfo(), - MachineMemOperand::MOStore, - VT.getStoreSize(), 4); - return DAG.getMemIntrinsicNode(Opcode, DL, - Op->getVTList(), Ops, VT, MMO); - } - case Intrinsic::amdgcn_tbuffer_store: { SDValue VData = Op.getOperand(2); bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16); diff --git a/llvm/lib/Target/AMDGPU/SIIntrinsics.td b/llvm/lib/Target/AMDGPU/SIIntrinsics.td index 3892f19d3df..e51ff4b4bc5 100644 --- a/llvm/lib/Target/AMDGPU/SIIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/SIIntrinsics.td @@ -16,22 +16,4 @@ let TargetPrefix = "SI", isTarget = 1 in { def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; - // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed - def int_SI_tbuffer_store : Intrinsic < - [], - [llvm_anyint_ty, // rsrc(SGPR) - llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32 - llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW - llvm_i32_ty, // vaddr(VGPR) - llvm_i32_ty, // soffset(SGPR) - llvm_i32_ty, // inst_offset(imm) - llvm_i32_ty, // dfmt(imm) - llvm_i32_ty, // nfmt(imm) - llvm_i32_ty, // offen(imm) - llvm_i32_ty, // idxen(imm) - llvm_i32_ty, // glc(imm) - llvm_i32_ty, // slc(imm) - llvm_i32_ty], // tfe(imm) - []>; - } // End TargetPrefix = "SI", isTarget = 1 |
