summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/DFAPacketizer.cpp2
-rw-r--r--llvm/lib/CodeGen/MachineCopyPropagation.cpp10
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp24
-rw-r--r--llvm/lib/CodeGen/ProcessImplicitDefs.cpp4
-rw-r--r--llvm/lib/CodeGen/ScheduleDAGInstrs.cpp8
-rw-r--r--llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp2
-rw-r--r--llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp4
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/R600Packetizer.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp16
-rw-r--r--llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp2
-rw-r--r--llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp3
-rw-r--r--llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp6
-rw-r--r--llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp4
-rw-r--r--llvm/lib/Target/Mips/MipsAsmPrinter.cpp5
-rw-r--r--llvm/lib/Target/Sparc/SparcAsmPrinter.cpp4
-rw-r--r--llvm/lib/Target/X86/X86FrameLowering.cpp3
21 files changed, 56 insertions, 55 deletions
diff --git a/llvm/lib/CodeGen/DFAPacketizer.cpp b/llvm/lib/CodeGen/DFAPacketizer.cpp
index 9e27fc9a27d..c8a3d381242 100644
--- a/llvm/lib/CodeGen/DFAPacketizer.cpp
+++ b/llvm/lib/CodeGen/DFAPacketizer.cpp
@@ -198,7 +198,7 @@ VLIWPacketizerList::~VLIWPacketizerList() {
void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineInstr *MI) {
if (CurrentPacketMIs.size() > 1) {
MachineInstr *MIFirst = CurrentPacketMIs.front();
- finalizeBundle(*MBB, MIFirst->getInstrIterator(), MI->getInstrIterator());
+ finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator());
}
CurrentPacketMIs.clear();
ResourceTracker->clearResources();
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index aef5db9ca8a..79240b3b94a 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -90,10 +90,8 @@ static bool NoInterveningSideEffect(const MachineInstr *CopyMI,
if (MI->getParent() != MBB)
return false;
- for (MachineBasicBlock::const_instr_iterator
- I = std::next(CopyMI->getInstrIterator()),
- E = MBB->instr_end(), E2 = MI->getInstrIterator();
- I != E && I != E2; ++I) {
+ for (MachineBasicBlock::const_iterator I = std::next(CopyMI->getIterator()),
+ E = MBB->end(), E2 = MI->getIterator(); I != E && I != E2; ++I) {
if (I->hasUnmodeledSideEffects() || I->isCall() ||
I->isTerminator())
return false;
@@ -165,8 +163,8 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
// Clear any kills of Def between CopyMI and MI. This extends the
// live range.
- for (MachineInstr &MMI :
- make_range(CopyMI->getInstrIterator(), MI->getInstrIterator()))
+ for (MachineInstr &MMI
+ : make_range(CopyMI->getIterator(), MI->getIterator()))
MMI.clearRegisterKills(Def, TRI);
MI->eraseFromParent();
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 86dbf7a3070..4103253133e 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -934,7 +934,7 @@ MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
assert(!isBundledWithPred() && "Must be called on bundle header");
- for (auto MII = getInstrIterator();; ++MII) {
+ for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
if (MII->getDesc().getFlags() & Mask) {
if (Type == AnyInBundle)
return true;
@@ -958,10 +958,10 @@ bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
if (isBundle()) {
// Both instructions are bundles, compare MIs inside the bundle.
- auto I1 = getInstrIterator();
- auto E1 = getParent()->instr_end();
- auto I2 = Other->getInstrIterator();
- auto E2 = Other->getParent()->instr_end();
+ MachineBasicBlock::const_instr_iterator I1 = getIterator();
+ MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
+ MachineBasicBlock::const_instr_iterator I2 = Other->getIterator();
+ MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
while (++I1 != E1 && I1->isInsideBundle()) {
++I2;
if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(&*I2, Check))
@@ -1069,7 +1069,8 @@ unsigned MachineInstr::getNumExplicitOperands() const {
void MachineInstr::bundleWithPred() {
assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
setFlag(BundledPred);
- auto Pred = --getInstrIterator();
+ MachineBasicBlock::instr_iterator Pred = getIterator();
+ --Pred;
assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
Pred->setFlag(BundledSucc);
}
@@ -1077,7 +1078,8 @@ void MachineInstr::bundleWithPred() {
void MachineInstr::bundleWithSucc() {
assert(!isBundledWithSucc() && "MI is already bundled with its successor");
setFlag(BundledSucc);
- auto Succ = ++getInstrIterator();
+ MachineBasicBlock::instr_iterator Succ = getIterator();
+ ++Succ;
assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
Succ->setFlag(BundledPred);
}
@@ -1085,7 +1087,8 @@ void MachineInstr::bundleWithSucc() {
void MachineInstr::unbundleFromPred() {
assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
clearFlag(BundledPred);
- auto Pred = --getInstrIterator();
+ MachineBasicBlock::instr_iterator Pred = getIterator();
+ --Pred;
assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
Pred->clearFlag(BundledSucc);
}
@@ -1093,7 +1096,8 @@ void MachineInstr::unbundleFromPred() {
void MachineInstr::unbundleFromSucc() {
assert(isBundledWithSucc() && "MI isn't bundled with its successor");
clearFlag(BundledSucc);
- auto Succ = ++getInstrIterator();
+ MachineBasicBlock::instr_iterator Succ = getIterator();
+ ++Succ;
assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
Succ->clearFlag(BundledPred);
}
@@ -1228,7 +1232,7 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
/// Return the number of instructions inside the MI bundle, not counting the
/// header instruction.
unsigned MachineInstr::getBundleSize() const {
- auto I = getInstrIterator();
+ MachineBasicBlock::const_instr_iterator I = getIterator();
unsigned Size = 0;
while (I->isBundledWithSucc()) {
++Size;
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index ea5d2345da4..d27ea2f5186 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -96,8 +96,8 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
// This is a physreg implicit-def.
// Look for the first instruction to use or define an alias.
- auto UserMI = MI->getInstrIterator();
- auto UserE = MI->getParent()->instr_end();
+ MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
+ MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
bool Found = false;
for (++UserMI; UserMI != UserE; ++UserMI) {
for (MachineOperand &MO : UserMI->operands()) {
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 46b1add34ba..aab3184c58a 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -1200,8 +1200,8 @@ static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg,
// Once we set a kill flag on an instruction, we bail out, as otherwise we
// might set it on too many operands. We will clear as many flags as we
// can though.
- auto Begin = MI->getInstrIterator();
- auto End = getBundleEnd(MI);
+ MachineBasicBlock::instr_iterator Begin = MI->getIterator();
+ MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
while (Begin != End) {
for (MachineOperand &MO : (--End)->operands()) {
if (!MO.isReg() || MO.isDef() || Reg != MO.getReg())
@@ -1334,8 +1334,8 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
toggleKillFlag(MI, MO);
DEBUG(MI->dump());
DEBUG(if (MI->getOpcode() == TargetOpcode::BUNDLE) {
- auto Begin = MI->getInstrIterator();
- auto End = getBundleEnd(MI);
+ MachineBasicBlock::instr_iterator Begin = MI->getIterator();
+ MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
while (++Begin != End)
DEBUG(Begin->dump());
});
diff --git a/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp b/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
index 6f915e6e1bc..9310ac4a44a 100644
--- a/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
@@ -118,7 +118,7 @@ struct LDTLSCleanup : public MachineFunctionPass {
// Insert a copy from X0 to TLSBaseAddrReg for later.
MachineInstr *Copy =
- BuildMI(*I->getParent(), ++I->getInstrIterator(), I->getDebugLoc(),
+ BuildMI(*I->getParent(), ++I->getIterator(), I->getDebugLoc(),
TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
.addReg(AArch64::X0);
diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
index 7eff318ebb8..8def8f32d70 100644
--- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -154,8 +154,8 @@ bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
MBB->addLiveIn(TargetReg);
// Clear any kills of TargetReg between CompBr and the last removed COPY.
- for (MachineInstr &MMI : make_range(MBB->begin()->getInstrIterator(),
- LastChange->getInstrIterator()))
+ for (MachineInstr &MMI :
+ make_range(MBB->begin()->getIterator(), LastChange->getIterator()))
MMI.clearRegisterKills(SmallestDef, TRI);
return true;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 9d1d25bb5d7..dfc652f31da 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -97,7 +97,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
#endif
if (MI->isBundle()) {
const MachineBasicBlock *MBB = MI->getParent();
- auto I = ++MI->getInstrIterator();
+ MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
while (I != MBB->instr_end() && I->isInsideBundle()) {
EmitInstruction(&*I);
++I;
diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
index bb4bda25470..b17b002f3b5 100644
--- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
@@ -397,7 +397,7 @@ private:
std::vector<int64_t> Literals;
if (I->isBundle()) {
MachineInstr *DeleteMI = I;
- MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
+ MachineBasicBlock::instr_iterator BI = I.getIterator();
while (++BI != E && BI->isBundledWithPred()) {
BI->unbundleFromPred();
for (unsigned i = 0, e = BI->getNumOperands(); i != e; ++i) {
diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp
index 21269613a30..63fba1fd061 100644
--- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp
@@ -75,7 +75,7 @@ private:
I--;
if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
return Result;
- MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
+ MachineBasicBlock::instr_iterator BI = I.getIterator();
if (I->isBundle())
BI++;
int LastDstChan = -1;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 832fd47bdcc..689a43e7df4 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -440,8 +440,8 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
if (MI->isBundle()) {
- auto I = MI->getInstrIterator();
- auto E = MI->getParent()->instr_end();
+ MachineBasicBlock::const_instr_iterator I = MI->getIterator();
+ MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
while (++I != E && I->isInsideBundle()) {
int PIdx = I->findFirstPredOperandIdx();
if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
@@ -647,8 +647,8 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
unsigned Size = 0;
- auto I = MI->getInstrIterator();
- auto E = MI->getParent()->instr_end();
+ MachineBasicBlock::const_instr_iterator I = MI->getIterator();
+ MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
while (++I != E && I->isInsideBundle()) {
assert(!I->isBundle() && "No nested bundle!");
Size += GetInstSizeInBytes(&*I);
@@ -3410,7 +3410,7 @@ static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
Dist = 0;
MachineBasicBlock::const_iterator I = MI; ++I;
- MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
+ MachineBasicBlock::const_instr_iterator II = std::prev(I.getIterator());
assert(II->isInsideBundle() && "Empty bundle?");
int Idx = -1;
@@ -3432,7 +3432,7 @@ static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
unsigned &UseIdx, unsigned &Dist) {
Dist = 0;
- auto II = ++MI->getInstrIterator();
+ MachineBasicBlock::const_instr_iterator II = ++MI->getIterator();
assert(II->isInsideBundle() && "Empty bundle?");
MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
@@ -3975,8 +3975,8 @@ unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
// other passes may query the latency of a bundled instruction.
if (MI->isBundle()) {
unsigned Latency = 0;
- auto I = MI->getInstrIterator();
- auto E = MI->getParent()->instr_end();
+ MachineBasicBlock::const_instr_iterator I = MI->getIterator();
+ MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
while (++I != E && I->isInsideBundle()) {
if (I->getOpcode() != ARM::t2IT)
Latency += getInstrLatency(ItinData, &*I, PredCost);
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 1c204e5fa7b..56f3498e120 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -731,7 +731,7 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
HI16.addImm(Pred).addReg(PredReg);
if (RequiresBundling)
- finalizeBundle(MBB, LO16->getInstrIterator(), MBBI->getInstrIterator());
+ finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
index 8c611b6f467..c28ebe9cb26 100644
--- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
+++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
@@ -256,8 +256,7 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
// Finalize the bundle.
- finalizeBundle(MBB, InsertPos.getInstrIterator(),
- ++LastITMI->getInstrIterator());
+ finalizeBundle(MBB, InsertPos.getIterator(), ++LastITMI->getIterator());
Modified = true;
++NumITs;
diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 53030832d90..48f3e3111a8 100644
--- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -591,7 +591,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
if (MI->isBundle()) {
const MachineBasicBlock* MBB = MI->getParent();
- auto MII = MI->getInstrIterator();
+ MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
unsigned IgnoreCount = 0;
for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 5294266d35f..a1e58e95371 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -582,7 +582,7 @@ namespace {
if (!It->isBundle())
return It->getOpcode() == Hexagon::S2_allocframe;
auto End = It->getParent()->instr_end();
- MachineBasicBlock::const_instr_iterator I = It.getInstrIterator();
+ MachineBasicBlock::const_instr_iterator I = It.getIterator();
while (++I != End && I->isBundled())
if (I->getOpcode() == Hexagon::S2_allocframe)
return true;
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 457626f9b2c..d20a809d6c0 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1295,7 +1295,7 @@ bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
// Out of order.
unsigned PredR = CmpI->getOperand(0).getReg();
bool FoundBump = false;
- instr_iterator CmpIt = CmpI->getInstrIterator(), NextIt = std::next(CmpIt);
+ instr_iterator CmpIt = CmpI->getIterator(), NextIt = std::next(CmpIt);
for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
MachineInstr *In = &*I;
for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
@@ -1307,7 +1307,7 @@ bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
}
if (In == BumpI) {
- BB->splice(++BumpI->getInstrIterator(), BB, CmpI->getInstrIterator());
+ BB->splice(++BumpI->getIterator(), BB, CmpI->getIterator());
FoundBump = true;
break;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index d827ec9ee1f..9a92f996069 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -520,7 +520,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// executed, so remove it.
if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
TBB = SecondLastInst->getOperand(0).getMBB();
- I = LastInst->getInstrIterator();
+ I = LastInst->getIterator();
if (AllowModify)
I->eraseFromParent();
return false;
@@ -1260,7 +1260,7 @@ bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
MI->addOperand(T->getOperand(i));
- auto TI = T->getInstrIterator();
+ MachineBasicBlock::instr_iterator TI = T->getIterator();
B.erase(TI);
MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
@@ -4071,7 +4071,7 @@ unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
unsigned HexagonInstrInfo::nonDbgBundleSize(
MachineBasicBlock::const_iterator BundleHead) const {
assert(BundleHead->isBundle() && "Not a bundle header");
- auto MII = BundleHead.getInstrIterator();
+ auto MII = BundleHead.getIterator();
// Skip the bundle header.
return nonDbgMICount(++MII, getBundleEnd(BundleHead));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 81850548bb6..1ce385ee68e 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -126,9 +126,9 @@ static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI,
MachineBasicBlock::iterator BundleIt, bool Before) {
MachineBasicBlock::instr_iterator InsertPt;
if (Before)
- InsertPt = BundleIt.getInstrIterator();
+ InsertPt = BundleIt.getIterator();
else
- InsertPt = std::next(BundleIt).getInstrIterator();
+ InsertPt = std::next(BundleIt).getIterator();
MachineBasicBlock &B = *MI->getParent();
// The instruction should at least be bundled with the preceding instruction
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 6c2d9830f4f..957529376b3 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -173,8 +173,9 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return;
}
- auto I = MI->getInstrIterator();
- auto E = MI->getParent()->instr_end();
+
+ MachineBasicBlock::const_instr_iterator I = MI->getIterator();
+ MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
do {
// Do any auto-generated pseudo lowerings.
diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
index 184db39732b..e3b0f526674 100644
--- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -267,8 +267,8 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
return;
}
- auto I = MI->getInstrIterator();
- auto E = MI->getParent()->instr_end();
+ MachineBasicBlock::const_instr_iterator I = MI->getIterator();
+ MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
do {
MCInst TmpInst;
LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index db802c3a7e3..378204f6c0c 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -464,8 +464,7 @@ void X86FrameLowering::inlineStackProbe(MachineFunction &MF,
if (ChkStkStub != nullptr) {
assert(!ChkStkStub->isBundled() &&
"Not expecting bundled instructions here");
- MachineBasicBlock::iterator MBBI =
- std::next(ChkStkStub->getInstrIterator());
+ MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
assert(std::prev(MBBI).operator==(ChkStkStub) &&
"MBBI expected after __chkstk_stub.");
DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
OpenPOWER on IntegriCloud