diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 34 |
1 files changed, 26 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index ba44e013d50..229346fdb82 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -664,6 +664,12 @@ static bool IsAnAddressOperand(const MachineOperand &MO) { llvm_unreachable("unhandled machine operand type"); } +static MachineOperand makeImplicit(const MachineOperand &MO) { + MachineOperand NewMO = MO; + NewMO.setImplicit(); + return NewMO; +} + void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) { MachineInstr &MI = *MBBI; @@ -698,6 +704,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); + if (isCC) + LO16.add(makeImplicit(MI.getOperand(1))); TransferImpOps(MI, LO16, HI16); MI.eraseFromParent(); return; @@ -751,6 +759,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, if (RequiresBundling) finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); + if (isCC) + LO16.add(makeImplicit(MI.getOperand(1))); TransferImpOps(MI, LO16, HI16); MI.eraseFromParent(); } @@ -1052,7 +1062,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, MI.getOperand(1).getReg()) .add(MI.getOperand(2)) .addImm(MI.getOperand(3).getImm()) // 'pred' - .add(MI.getOperand(4)); + .add(MI.getOperand(4)) + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; @@ -1065,7 +1076,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, .add(MI.getOperand(2)) .addImm(MI.getOperand(3).getImm()) // 'pred' .add(MI.getOperand(4)) - .add(condCodeOp()); // 's' bit + .add(condCodeOp()) // 's' bit + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; @@ -1077,7 +1089,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, .addImm(MI.getOperand(3).getImm()) .addImm(MI.getOperand(4).getImm()) // 'pred' .add(MI.getOperand(5)) - .add(condCodeOp()); // 's' bit + .add(condCodeOp()) // 's' bit + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; @@ -1090,7 +1103,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, .addImm(MI.getOperand(4).getImm()) .addImm(MI.getOperand(5).getImm()) // 'pred' .add(MI.getOperand(6)) - .add(condCodeOp()); // 's' bit + .add(condCodeOp()) // 's' bit + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; @@ -1102,7 +1116,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, MI.getOperand(1).getReg()) .addImm(MI.getOperand(2).getImm()) .addImm(MI.getOperand(3).getImm()) // 'pred' - .add(MI.getOperand(4)); + .add(MI.getOperand(4)) + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; } @@ -1114,7 +1129,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, .addImm(MI.getOperand(2).getImm()) .addImm(MI.getOperand(3).getImm()) // 'pred' .add(MI.getOperand(4)) - .add(condCodeOp()); // 's' bit + .add(condCodeOp()) // 's' bit + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; @@ -1127,7 +1143,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, .addImm(MI.getOperand(2).getImm()) .addImm(MI.getOperand(3).getImm()) // 'pred' .add(MI.getOperand(4)) - .add(condCodeOp()); // 's' bit + .add(condCodeOp()) // 's' bit + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; @@ -1150,7 +1167,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, .addImm(MI.getOperand(3).getImm()) .addImm(MI.getOperand(4).getImm()) // 'pred' .add(MI.getOperand(5)) - .add(condCodeOp()); // 's' bit + .add(condCodeOp()) // 's' bit + .add(makeImplicit(MI.getOperand(1))); MI.eraseFromParent(); return true; } |
