diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSchedule.td | 4 |
3 files changed, 8 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 8967e99d196..b8d8aa0ce20 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -789,7 +789,7 @@ class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd, class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>; class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd, - II_MTC0>; + II_MTHC0>; class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTC1>, HARDFLOAT, FGR_32; @@ -838,7 +838,7 @@ class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd, class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>; class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd, - II_MFC0>; + II_MFHC0>; class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, HARDFLOAT, FGR_32; class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd, diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index 98caf08f93b..670272d47e9 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -59,6 +59,7 @@ include "MipsCallingConv.td" // Avoid forward declaration issues. include "MipsScheduleP5600.td" +include "MipsScheduleGeneric.td" def MipsInstrInfo : InstrInfo; @@ -191,7 +192,7 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", "The P5600 Processor", [FeatureMips32r5]>; class Proc<string Name, list<SubtargetFeature> Features> - : Processor<Name, MipsGenericItineraries, Features>; + : ProcessorModel<Name, MipsGenericModel, Features>; def : Proc<"mips1", [FeatureMips1]>; def : Proc<"mips2", [FeatureMips2]>; diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td index 8478fa843d8..76bd818a4f1 100644 --- a/llvm/lib/Target/Mips/MipsSchedule.td +++ b/llvm/lib/Target/Mips/MipsSchedule.td @@ -216,6 +216,7 @@ def II_MIN_S : InstrItinClass; def II_MINA_D : InstrItinClass; def II_MINA_S : InstrItinClass; def II_MFC0 : InstrItinClass; +def II_MFHC0 : InstrItinClass; def II_MFC1 : InstrItinClass; def II_MFHC1 : InstrItinClass; def II_MFC2 : InstrItinClass; @@ -244,6 +245,7 @@ def II_MSUB_S : InstrItinClass; def II_MSUBF_D : InstrItinClass; def II_MSUBF_S : InstrItinClass; def II_MTC0 : InstrItinClass; +def II_MTHC0 : InstrItinClass; def II_MTC1 : InstrItinClass; def II_MTHC1 : InstrItinClass; def II_MTC2 : InstrItinClass; @@ -640,9 +642,11 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_DMTC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>, |
