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-rw-r--r--llvm/lib/Target/AMDGPU/VOP1Instructions.td8
-rw-r--r--llvm/lib/Target/AMDGPU/VOP2Instructions.td15
-rw-r--r--llvm/lib/Target/AMDGPU/VOPCInstructions.td5
-rw-r--r--llvm/lib/Target/AMDGPU/VOPInstructions.td3
4 files changed, 26 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 211922c8c21..9d876c39674 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -56,6 +56,9 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
let isPseudo = 0;
let isCodeGenOnly = 0;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
+
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
@@ -212,7 +215,6 @@ def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> {
let Outs = (outs);
let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0);
let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0);
-
let InsDPP = (ins Src0RC32:$vdst, Src0RC32:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
let InsSDWA = (ins Src0RC32:$vdst, Int32InputMods:$src0_modifiers, VCSrc_b32:$src0,
@@ -426,6 +428,8 @@ class VOP1_SDWA <bits<8> op, VOP1_Pseudo ps, VOPProfile P = ps.Pfl> :
let Uses = ps.Uses;
let SchedRW = ps.SchedRW;
let hasSideEffects = ps.hasSideEffects;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
let AsmMatchConverter = "cvtSdwaVOP1";
bits<8> vdst;
@@ -441,6 +445,8 @@ class VOP1_DPP <bits<8> op, VOP1_Pseudo ps, VOPProfile P = ps.Pfl> :
let Uses = ps.Uses;
let SchedRW = ps.SchedRW;
let hasSideEffects = ps.hasSideEffects;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
bits<8> vdst;
let Inst{8-0} = 0xfa; // dpp
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 64e2bf217ed..a3025ffe2b3 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -72,6 +72,9 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
let isPseudo = 0;
let isCodeGenOnly = 0;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
+
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
@@ -157,13 +160,13 @@ class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
HasModifiers, Src0Mod, Src1Mod, Src2Mod>.ret;
- let InsDPP = (ins FP32InputMods:$src0_modifiers, Src0RC32:$src0,
- FP32InputMods:$src1_modifiers, Src1RC32:$src1,
+ let InsDPP = (ins FP32InputMods:$src0_modifiers, Src0DPP:$src0,
+ FP32InputMods:$src1_modifiers, Src1DPP:$src1,
VGPR_32:$src2, // stub argument
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsSDWA = (ins FP32InputMods:$src0_modifiers, Src0RC32:$src0,
- FP32InputMods:$src1_modifiers, Src1RC32:$src1,
+ let InsSDWA = (ins FP32InputMods:$src0_modifiers, Src0SDWA:$src0,
+ FP32InputMods:$src1_modifiers, Src1SDWA:$src1,
VGPR_32:$src2, // stub argument
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
src0_sel:$src0_sel, src1_sel:$src1_sel);
@@ -557,6 +560,8 @@ class VOP2_SDWA <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
let Uses = ps.Uses;
let SchedRW = ps.SchedRW;
let hasSideEffects = ps.hasSideEffects;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
let AsmMatchConverter = "cvtSdwaVOP2";
bits<8> vdst;
@@ -574,6 +579,8 @@ class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
let Uses = ps.Uses;
let SchedRW = ps.SchedRW;
let hasSideEffects = ps.hasSideEffects;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
bits<8> vdst;
bits<8> src1;
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 55ebd9448dc..32137888ef1 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -71,6 +71,9 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
let isPseudo = 0;
let isCodeGenOnly = 0;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
+
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
@@ -826,6 +829,8 @@ class VOPC_SDWA<bits<8> op, VOPC_Pseudo ps, VOPProfile P = ps.Pfl> :
let AsmMatchConverter = "cvtSdwaVOPC";
let isCompare = ps.isCompare;
let isCommutable = ps.isCommutable;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
bits<8> src1;
let Inst{8-0} = 0xf9; // sdwa
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index b56ac2fe323..3af16b32695 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -118,6 +118,9 @@ class VOP3_Real <VOP3_Pseudo ps, int EncodingFamily> :
let isPseudo = 0;
let isCodeGenOnly = 0;
+ let Constraints = ps.Constraints;
+ let DisableEncoding = ps.DisableEncoding;
+
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
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