diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 32 |
2 files changed, 23 insertions, 23 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 047b3c30a4e..0f5c7f36903 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -5097,15 +5097,15 @@ let Predicates = [HasAVX512] in { multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNode> { defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), - (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr, + (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", - (_.VT (OpNode (_Src.VT _Src.RC:$src1), + (_.VT (OpNode (_.VT _.RC:$src1), (_Src.VT _Src.RC:$src2)))>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>; defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst), (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", - (_.VT (OpNode (_Src.VT _Src.RC:$src1), + (_.VT (OpNode (_.VT _.RC:$src1), (_Src.VT (scalar_to_vector (_Src.ScalarLdFrag addr:$src2)))))>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>; @@ -5115,9 +5115,9 @@ multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _ multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd> { defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), - (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr, + (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr, "{sae}, $src2, $src1", "$src1, $src2, {sae}", - (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1), + (_.VT (OpNodeRnd (_.VT _.RC:$src1), (_Src.VT _Src.RC:$src2), (i32 FROUND_NO_EXC)))>, EVEX_4V, VEX_LIG, EVEX_B; @@ -5127,9 +5127,9 @@ multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTIn multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd> { defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), - (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr, + (ins _.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr, "$rc, $src2, $src1", "$src1, $src2, $rc", - (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1), + (_.VT (OpNodeRnd (_.VT _.RC:$src1), (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_B, EVEX_RC; diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index f3092f51a14..670af0d1b46 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -149,32 +149,32 @@ def X86vfpround: SDNode<"X86ISD::VFPROUND", SDTCisOpSmallerThanOp<0, 1>]>>; def X86fround: SDNode<"X86ISD::VFPROUND", - SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>, - SDTCVecEltisVT<0, f32>, - SDTCVecEltisVT<1, f64>, + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, + SDTCisSameAs<0, 1>, SDTCVecEltisVT<2, f64>, - SDTCisOpSmallerThanOp<0, 1>]>>; + SDTCisSameSizeAs<0, 2>, + SDTCisOpSmallerThanOp<0, 2>]>>; def X86froundRnd: SDNode<"X86ISD::VFPROUND", - SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>, - SDTCVecEltisVT<0, f32>, - SDTCVecEltisVT<1, f64>, + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, + SDTCisSameAs<0, 1>, SDTCVecEltisVT<2, f64>, - SDTCisOpSmallerThanOp<0, 1>, + SDTCisSameSizeAs<0, 2>, + SDTCisOpSmallerThanOp<0, 2>, SDTCisInt<3>]>>; def X86fpext : SDNode<"X86ISD::VFPEXT", - SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>, - SDTCVecEltisVT<0, f64>, - SDTCVecEltisVT<1, f32>, + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, + SDTCisSameAs<0, 1>, SDTCVecEltisVT<2, f32>, - SDTCisOpSmallerThanOp<1, 0>]>>; + SDTCisSameSizeAs<0, 2>, + SDTCisOpSmallerThanOp<2, 0>]>>; def X86fpextRnd : SDNode<"X86ISD::VFPEXT", - SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>, - SDTCVecEltisVT<0, f64>, - SDTCVecEltisVT<1, f32>, + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>, + SDTCisSameAs<0, 1>, SDTCVecEltisVT<2, f32>, - SDTCisOpSmallerThanOp<1, 0>, + SDTCisSameSizeAs<0, 2>, + SDTCisOpSmallerThanOp<2, 0>, SDTCisInt<3>]>>; def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>; |
