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-rw-r--r--llvm/lib/CodeGen/RenameIndependentSubregs.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index cc32e43968b..6923716e10c 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -243,6 +243,11 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
unsigned VReg = Intervals[ID]->reg;
MO.setReg(VReg);
+ if (MO.isTied()) {
+ /// Undef use operands are not tracked in the equivalence class but need
+ /// to be update if they are tied.
+ MO.getParent()->substituteRegister(Reg, VReg, 0, TRI);
+ }
}
// TODO: We could attempt to recompute new register classes while visiting
// the operands: Some of the split register may be fine with less constraint
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