diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 29 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 14 |
2 files changed, 32 insertions, 11 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 7e2b152395a..9d775ec8d5f 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -875,10 +875,10 @@ let Predicates = [HasSVE] in { defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; // Predicated shifts - defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; - defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; - defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; - defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; + defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">; + defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">; + defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">; + defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd">; defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; @@ -1150,6 +1150,20 @@ let Predicates = [HasSVE2] in { defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">; defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">; + // SVE2 saturating/rounding bitwise shift left (predicated) + defm SRSHL_ZPmZ : sve2_int_arith_pred<0b000100, "srshl">; + defm URSHL_ZPmZ : sve2_int_arith_pred<0b000110, "urshl">; + defm SRSHLR_ZPmZ : sve2_int_arith_pred<0b001100, "srshlr">; + defm URSHLR_ZPmZ : sve2_int_arith_pred<0b001110, "urshlr">; + defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl">; + defm UQSHL_ZPmZ : sve2_int_arith_pred<0b010010, "uqshl">; + defm SQRSHL_ZPmZ : sve2_int_arith_pred<0b010100, "sqrshl">; + defm UQRSHL_ZPmZ : sve2_int_arith_pred<0b010110, "uqrshl">; + defm SQSHLR_ZPmZ : sve2_int_arith_pred<0b011000, "sqshlr">; + defm UQSHLR_ZPmZ : sve2_int_arith_pred<0b011010, "uqshlr">; + defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">; + defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">; + // SVE2 integer multiply long defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; @@ -1157,4 +1171,11 @@ let Predicates = [HasSVE2] in { defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">; defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">; defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">; + + // Predicated shifts + defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; + defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; + defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">; + defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">; + defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">; } diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index ac4d800197b..8b4c00935e5 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -2926,9 +2926,9 @@ multiclass sve_int_index_rr<string asm> { //===----------------------------------------------------------------------===// // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, - ZPRRegOp zprty, Operand immtype, - ElementSizeEnum size> +class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm, + ZPRRegOp zprty, Operand immtype, + ElementSizeEnum size> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", "", @@ -2938,8 +2938,8 @@ class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, bits<6> imm; let Inst{31-24} = 0b00000100; let Inst{23-22} = tsz8_64{3-2}; - let Inst{21-19} = 0b000; - let Inst{18-16} = opc; + let Inst{21-20} = 0b00; + let Inst{19-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-8} = tsz8_64{1-0}; @@ -2951,7 +2951,7 @@ class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, let ElementSize = size; } -multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, @@ -2969,7 +2969,7 @@ multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> { } } -multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> { +multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, |
