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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/FastISel.cpp4
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp11
-rw-r--r--llvm/lib/Target/X86/X86FastISel.cpp6
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp3
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.h2
5 files changed, 18 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 3139cb3bc7f..4b773226072 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -450,7 +450,7 @@ FastISel::SelectOperator(User *I, unsigned Opcode) {
UpdateValueMap(I, Reg);
return true;
}
-
+
default:
// Unhandled instruction. Halt "fast" selection and bail.
return false;
@@ -458,6 +458,7 @@ FastISel::SelectOperator(User *I, unsigned Opcode) {
}
FastISel::FastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am)
@@ -466,6 +467,7 @@ FastISel::FastISel(MachineFunction &mf,
MBBMap(bm),
StaticAllocaMap(am),
MF(mf),
+ MMI(mmi),
MRI(MF.getRegInfo()),
MFI(*MF.getFrameInfo()),
MCP(*MF.getConstantPool()),
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index c2938e35f88..c1e80fc7889 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -309,7 +309,8 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
DOUT << "\n\n\n=== " << Fn.getName() << "\n";
FuncInfo->set(Fn, MF, EnableFastISel);
- CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>());
+ MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
+ CurDAG->init(MF, MMI);
SDL->init(GFI, *AA);
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
@@ -317,7 +318,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
// Mark landing pad.
FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
- SelectAllBasicBlocks(Fn, MF);
+ SelectAllBasicBlocks(Fn, MF, MMI);
// If the first basic block in the function has live ins that need to be
// copied into vregs, emit the copies into the top of the block before
@@ -710,7 +711,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(BB->dump());
}
-void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) {
+void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
+ MachineModuleInfo *MMI) {
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
BasicBlock *LLVMBB = &*I;
BB = FuncInfo->MBBMap[LLVMBB];
@@ -726,7 +728,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) {
// Before doing SelectionDAG ISel, see if FastISel has been requested.
// FastISel doesn't support EH landing pads, which require special handling.
if (EnableFastISel && !BB->isLandingPad()) {
- if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, FuncInfo->ValueMap,
+ if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, MMI,
+ FuncInfo->ValueMap,
FuncInfo->MBBMap,
FuncInfo->StaticAllocaMap)) {
// Emit code for any incoming arguments. This must happen before
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 7747788e813..b53e042edcb 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -49,10 +49,11 @@ class X86FastISel : public FastISel {
public:
explicit X86FastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am)
- : FastISel(mf, vm, bm, am) {
+ : FastISel(mf, mmi, vm, bm, am) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
X86ScalarSSEf64 = Subtarget->hasSSE2();
@@ -1160,9 +1161,10 @@ unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
namespace llvm {
llvm::FastISel *X86::createFastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am) {
- return new X86FastISel(mf, vm, bm, am);
+ return new X86FastISel(mf, mmi, vm, bm, am);
}
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f988048a106..18d0f6c78ca 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1866,12 +1866,13 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
FastISel *
X86TargetLowering::createFastISel(MachineFunction &mf,
+ MachineModuleInfo *mmo,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *,
MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am) {
- return X86::createFastISel(mf, vm, bm, am);
+ return X86::createFastISel(mf, mmo, vm, bm, am);
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 96d829c583e..875787a53aa 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -472,6 +472,7 @@ namespace llvm {
/// or null if the target does not support "fast" ISel.
virtual FastISel *
createFastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &,
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
DenseMap<const AllocaInst *, int> &);
@@ -604,6 +605,7 @@ namespace llvm {
namespace X86 {
FastISel *createFastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &,
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
DenseMap<const AllocaInst *, int> &);
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