diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 45 |
2 files changed, 51 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2a8dde28f78..8ebe0cea234 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -135,6 +135,8 @@ let Predicates = [HasSVE] in { defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">; defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">; + defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">; + defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; @@ -199,6 +201,10 @@ let Predicates = [HasSVE] in { def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">; def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">; + def FEXPA_ZZ_H : sve_int_bin_cons_misc_0_c<0b01000000, "fexpa", ZPR16>; + def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>; + def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>; + def AND_PPzPP : sve_int_pred_log<0b0000, "and">; def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">; def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index cb2cb12788f..a82598c320d 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -3959,3 +3959,48 @@ multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> { def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>; def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>; } + + +//===----------------------------------------------------------------------===// +// SVE Integer Misc - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b101100; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_bin_cons_misc_0_b<string asm> { + def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>; + def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>; + def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>; +} + +class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn), + asm, "\t$Zd, $Zn", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{7-6}; + let Inst{21} = 0b1; + let Inst{20-16} = opc{5-1}; + let Inst{15-11} = 0b10111; + let Inst{10} = opc{0}; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +}
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