diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 76 |
2 files changed, 98 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index da26b409a45..739fb2a73b1 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1268,6 +1268,21 @@ let Predicates = [HasSVE2] in { defm MATCH_PPzZZ : sve2_char_match<0b0, "match">; defm NMATCH_PPzZZ : sve2_char_match<0b1, "nmatch">; + // SVE2 bitwise exclusive-or interleaved + defm EORBT_ZZZ : sve2_bitwise_xor_interleaved<0b0, "eorbt">; + defm EORTB_ZZZ : sve2_bitwise_xor_interleaved<0b1, "eortb">; + + // SVE2 bitwise shift left long + defm SSHLLB_ZZI : sve2_bitwise_shift_left_long<0b00, "sshllb">; + defm SSHLLT_ZZI : sve2_bitwise_shift_left_long<0b01, "sshllt">; + defm USHLLB_ZZI : sve2_bitwise_shift_left_long<0b10, "ushllb">; + defm USHLLT_ZZI : sve2_bitwise_shift_left_long<0b11, "ushllt">; + + // SVE2 integer add/subtract interleaved long + defm SADDLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b00, "saddlbt">; + defm SSUBLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b10, "ssublbt">; + defm SSUBLTB_ZZZ : sve2_misc_int_addsub_long_interleaved<0b11, "ssubltb">; + // Predicated shifts defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; @@ -1285,3 +1300,10 @@ let Predicates = [HasSVE2AES] in { def PMULLT_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11011, "pmullt", ZPR128, ZPR64, ZPR64>; } + +let Predicates = [HasSVE2BitPerm] in { + // SVE2 bitwise permute + defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext">; + defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep">; + defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp">; +} diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index a05533b18da..61155c96c27 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -2192,6 +2192,82 @@ multiclass sve2_pmul_long<bits<1> opc, string asm> { } //===----------------------------------------------------------------------===// +// SVE2 Misc Group +//===----------------------------------------------------------------------===// + +class sve2_misc<bits<2> sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15-14} = 0b10; + let Inst{13-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_misc_bitwise<bits<4> opc, string asm> { + def _B : sve2_misc<0b00, opc, asm, ZPR8, ZPR8>; + def _H : sve2_misc<0b01, opc, asm, ZPR16, ZPR16>; + def _S : sve2_misc<0b10, opc, asm, ZPR32, ZPR32>; + def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>; +} + +multiclass sve2_bitwise_xor_interleaved<bit opc, string asm> { + let DestructiveInstType = Destructive, ElementSize = ElementSizeNone in { + def _B : sve2_misc<0b00, { 0b010, opc }, asm, ZPR8, ZPR8>; + def _H : sve2_misc<0b01, { 0b010, opc }, asm, ZPR16, ZPR16>; + def _S : sve2_misc<0b10, { 0b010, opc }, asm, ZPR32, ZPR32>; + def _D : sve2_misc<0b11, { 0b010, opc }, asm, ZPR64, ZPR64>; + } +} + +multiclass sve2_misc_int_addsub_long_interleaved<bits<2> opc, string asm> { + def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>; + def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>; + def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>; +} + +class sve2_bitwise_shift_left_long<bits<3> tsz8_64, bits<2> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + Operand immtype> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm), + asm, "\t$Zd, $Zn, $imm", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> imm; + let Inst{31-23} = 0b010001010; + let Inst{22} = tsz8_64{2}; + let Inst{21} = 0b0; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-16} = imm{2-0}; // imm3 + let Inst{15-12} = 0b1010; + let Inst{11-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_bitwise_shift_left_long<bits<2> opc, string asm> { + def _H : sve2_bitwise_shift_left_long<{0,0,1}, opc, asm, + ZPR16, ZPR8, vecshiftL8>; + def _S : sve2_bitwise_shift_left_long<{0,1,?}, opc, asm, + ZPR32, ZPR16, vecshiftL16> { + let Inst{19} = imm{3}; + } + def _D : sve2_bitwise_shift_left_long<{1,?,?}, opc, asm, + ZPR64, ZPR32, vecshiftL32> { + let Inst{20-19} = imm{4-3}; + } +} + +//===----------------------------------------------------------------------===// // SVE2 Accumulate Group //===----------------------------------------------------------------------===// |
