diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 39 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 3 |
3 files changed, 36 insertions, 11 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index f4d13932a51..b0b0a8716b6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -477,12 +477,18 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, default: llvm_unreachable("Unknown size for regclass"); } - } else { // The spill of D tuples is implemented by Q tuples - if (RC == &AArch64::QPairRegClass) + } else { // For a super register class has more than one sub registers + if (AArch64::DPairRegClass.hasSubClassEq(RC)) + StoreOp = AArch64::ST1x2_8B; + else if (AArch64::DTripleRegClass.hasSubClassEq(RC)) + StoreOp = AArch64::ST1x3_8B; + else if (AArch64::DQuadRegClass.hasSubClassEq(RC)) + StoreOp = AArch64::ST1x4_8B; + else if (AArch64::QPairRegClass.hasSubClassEq(RC)) StoreOp = AArch64::ST1x2_16B; - else if (RC == &AArch64::QTripleRegClass) + else if (AArch64::QTripleRegClass.hasSubClassEq(RC)) StoreOp = AArch64::ST1x3_16B; - else if (RC == &AArch64::QQuadRegClass) + else if (AArch64::QQuadRegClass.hasSubClassEq(RC)) StoreOp = AArch64::ST1x4_16B; else llvm_unreachable("Unknown reg class"); @@ -537,12 +543,18 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, default: llvm_unreachable("Unknown size for regclass"); } - } else { // The spill of D tuples is implemented by Q tuples - if (RC == &AArch64::QPairRegClass) + } else { // For a super register class has more than one sub registers + if (AArch64::DPairRegClass.hasSubClassEq(RC)) + LoadOp = AArch64::LD1x2_8B; + else if (AArch64::DTripleRegClass.hasSubClassEq(RC)) + LoadOp = AArch64::LD1x3_8B; + else if (AArch64::DQuadRegClass.hasSubClassEq(RC)) + LoadOp = AArch64::LD1x4_8B; + else if (AArch64::QPairRegClass.hasSubClassEq(RC)) LoadOp = AArch64::LD1x2_16B; - else if (RC == &AArch64::QTripleRegClass) + else if (AArch64::QTripleRegClass.hasSubClassEq(RC)) LoadOp = AArch64::LD1x3_16B; - else if (RC == &AArch64::QQuadRegClass) + else if (AArch64::QQuadRegClass.hasSubClassEq(RC)) LoadOp = AArch64::LD1x4_16B; else llvm_unreachable("Unknown reg class"); @@ -649,6 +661,17 @@ void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI, MinOffset = -0x40 * AccessScale; MaxOffset = 0x3f * AccessScale; return; + case AArch64::LD1x2_8B: case AArch64::ST1x2_8B: + AccessScale = 16; + MinOffset = 0; + MaxOffset = 0xfff * AccessScale; + return; + case AArch64::LD1x3_8B: case AArch64::ST1x3_8B: + AccessScale = 24; + MinOffset = 0; + MaxOffset = 0xfff * AccessScale; + return; + case AArch64::LD1x4_8B: case AArch64::ST1x4_8B: case AArch64::LD1x2_16B: case AArch64::ST1x2_16B: AccessScale = 32; MinOffset = 0; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 618f6fb9289..973faf7363a 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -77,7 +77,10 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { } static bool hasFrameOffset(int opcode) { - return opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B && + return opcode != AArch64::LD1x2_8B && opcode != AArch64::LD1x3_8B && + opcode != AArch64::LD1x4_8B && opcode != AArch64::ST1x2_8B && + opcode != AArch64::ST1x3_8B && opcode != AArch64::ST1x4_8B && + opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B && opcode != AArch64::LD1x4_16B && opcode != AArch64::ST1x2_16B && opcode != AArch64::ST1x3_16B && opcode != AArch64::ST1x4_16B; } diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td index 8b1a9cb9074..cfc0c953bd2 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -30,7 +30,6 @@ def dsub_0 : SubRegIndex<64>; def dsub_1 : SubRegIndex<64, 64>; def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>; def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>; -def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>; } // Registers are identified with 5-bit ID numbers. @@ -206,7 +205,7 @@ def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> { //===----------------------------------------------------------------------===// // Consecutive vector registers //===----------------------------------------------------------------------===// -// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D30_D31 +// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0 def Tuples2D : RegisterTuples<[dsub_0, dsub_1], [(rotl FPR64, 0), (rotl FPR64, 1)]>; |
