diff options
Diffstat (limited to 'llvm/lib')
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 84 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 74 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 34 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 82 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 86 |
5 files changed, 84 insertions, 276 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 4d39cdfd7c3..ca16bc35ba2 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -211,27 +211,35 @@ def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort16, BWPort5, BWPort23]> { // AES instructions. def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption. let Latency = 7; + let NumMicroOps = 1; let ResourceCycles = [1]; } def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> { - let Latency = 7; - let ResourceCycles = [1, 1]; + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } + def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn. let Latency = 14; + let NumMicroOps = 2; let ResourceCycles = [2]; } def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> { - let Latency = 14; - let ResourceCycles = [2, 1]; + let Latency = 19; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5]> { // Key Generation. - let Latency = 10; - let ResourceCycles = [2, 8]; + +def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation. + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; } -def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23]> { - let Latency = 10; - let ResourceCycles = [2, 7, 1]; +def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> { + let Latency = 33; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; } // Carry-less multiplication instructions. @@ -2148,20 +2156,6 @@ def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { } def: InstRW<[BWWriteResGroup71], (instregex "STD")>; -def BWWriteResGroup72 : SchedWriteRes<[BWPort5]> { - let Latency = 7; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[BWWriteResGroup72], (instregex "AESDECLASTrr", - "AESDECrr", - "AESENCLASTrr", - "AESENCrr", - "VAESDECLASTrr", - "VAESDECrr", - "VAESENCLASTrr", - "VAESENCrr")>; - def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { let Latency = 7; let NumMicroOps = 2; @@ -3021,20 +3015,6 @@ def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; -def BWWriteResGroup134 : SchedWriteRes<[BWPort5,BWPort23]> { - let Latency = 12; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[BWWriteResGroup134], (instregex "AESDECLASTrm", - "AESDECrm", - "AESENCLASTrm", - "AESENCrm", - "VAESDECLASTrm", - "VAESDECrm", - "VAESENCLASTrm", - "VAESENCrm")>; - def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { let Latency = 12; let NumMicroOps = 3; @@ -3083,13 +3063,6 @@ def: InstRW<[BWWriteResGroup139], (instregex "DIVPDrr", "VSQRTPSr", "VSQRTSSr")>; -def BWWriteResGroup140 : SchedWriteRes<[BWPort5]> { - let Latency = 14; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[BWWriteResGroup140], (instregex "(V?)AESIMCrr")>; - def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { let Latency = 14; let NumMicroOps = 3; @@ -3252,13 +3225,6 @@ def: InstRW<[BWWriteResGroup161], (instregex "DIVPDrm", "VSQRTPSm", "VSQRTSSm")>; -def BWWriteResGroup162 : SchedWriteRes<[BWPort5,BWPort23]> { - let Latency = 19; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[BWWriteResGroup162], (instregex "(V?)AESIMCrm")>; - def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { let Latency = 19; let NumMicroOps = 5; @@ -3470,13 +3436,6 @@ def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156 } def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>; -def BWWriteResGroup184 : SchedWriteRes<[BWPort0,BWPort5,BWPort015]> { - let Latency = 29; - let NumMicroOps = 11; - let ResourceCycles = [2,7,2]; -} -def: InstRW<[BWWriteResGroup184], (instregex "(V?)AESKEYGENASSIST128rr")>; - def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { let Latency = 29; let NumMicroOps = 27; @@ -3498,13 +3457,6 @@ def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> } def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>; -def BWWriteResGroup188 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015]> { - let Latency = 33; - let NumMicroOps = 11; - let ResourceCycles = [2,7,1,1]; -} -def: InstRW<[BWWriteResGroup188], (instregex "(V?)AESKEYGENASSIST128rm")>; - def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> { let Latency = 34; let NumMicroOps = 3; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index fe0f1957a70..ffcd439d62f 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -210,29 +210,35 @@ def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> { // AES Instructions. def : WriteRes<WriteAESDecEnc, [HWPort5]> { let Latency = 7; + let NumMicroOps = 1; let ResourceCycles = [1]; } def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> { - let Latency = 7; - let ResourceCycles = [1, 1]; + let Latency = 13; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } def : WriteRes<WriteAESIMC, [HWPort5]> { let Latency = 14; + let NumMicroOps = 2; let ResourceCycles = [2]; } def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> { - let Latency = 14; - let ResourceCycles = [2, 1]; + let Latency = 20; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> { - let Latency = 10; - let ResourceCycles = [2, 8]; +def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> { + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; } -def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> { - let Latency = 10; - let ResourceCycles = [2, 7, 1]; +def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> { + let Latency = 34; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; } // Carry-less multiplication instructions. @@ -2833,26 +2839,6 @@ def HWWriteResGroup109 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPo def: InstRW<[HWWriteResGroup109], (instregex "SHLD(16|32|64)mrCL", "SHRD(16|32|64)mrCL")>; -def HWWriteResGroup110 : SchedWriteRes<[HWPort5]> { - let Latency = 7; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[HWWriteResGroup110], (instregex "VAESDECLASTrr", - "VAESDECrr", - "VAESENCLASTrr", - "VAESENCrr")>; - -def HWWriteResGroup111 : SchedWriteRes<[HWPort5,HWPort23]> { - let Latency = 13; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[HWWriteResGroup111], (instregex "(V?)AESDECLASTrm", - "(V?)AESDECrm", - "(V?)AESENCLASTrm", - "(V?)AESENCrm")>; - def HWWriteResGroup112 : SchedWriteRes<[HWPort0,HWPort5]> { let Latency = 7; let NumMicroOps = 3; @@ -3065,13 +3051,6 @@ def: InstRW<[HWWriteResGroup136], (instregex "DIVPDrr", "VSQRTPSr", "VSQRTSSr")>; -def HWWriteResGroup137 : SchedWriteRes<[HWPort5]> { - let Latency = 14; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[HWWriteResGroup137], (instregex "(V?)AESIMCrr")>; - def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort23]> { let Latency = 20; let NumMicroOps = 2; @@ -3080,13 +3059,6 @@ def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort23]> { def: InstRW<[HWWriteResGroup138], (instregex "DIVPDrm", "VSQRTPSm")>; -def HWWriteResGroup139 : SchedWriteRes<[HWPort5,HWPort23]> { - let Latency = 20; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[HWWriteResGroup139], (instregex "(V?)AESIMCrm")>; - def HWWriteResGroup140 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> { let Latency = 14; let NumMicroOps = 4; @@ -3312,20 +3284,6 @@ def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI16m", "DIV_FI32m")>; -def HWWriteResGroup167 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015]> { - let Latency = 34; - let NumMicroOps = 11; - let ResourceCycles = [2,7,1,1]; -} -def: InstRW<[HWWriteResGroup167], (instregex "(V?)AESKEYGENASSIST128rm")>; - -def HWWriteResGroup168 : SchedWriteRes<[HWPort0,HWPort5,HWPort015]> { - let Latency = 29; - let NumMicroOps = 11; - let ResourceCycles = [2,7,2]; -} -def: InstRW<[HWWriteResGroup168], (instregex "(V?)AESKEYGENASSIST128rr")>; - def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { let Latency = 35; let NumMicroOps = 23; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 1a8df415437..5c6a725c094 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -1266,16 +1266,6 @@ def: InstRW<[SBWriteResGroup56], (instregex "(V?)ANDNPDrm", "(V?)XORPDrm", "(V?)XORPSrm")>; -def SBWriteResGroup57 : SchedWriteRes<[SBPort5,SBPort015]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup57], (instregex "(V?)AESDECLASTrr", - "(V?)AESDECrr", - "(V?)AESENCLASTrr", - "(V?)AESENCrr")>; - def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { let Latency = 7; let NumMicroOps = 2; @@ -1962,13 +1952,6 @@ def: InstRW<[SBWriteResGroup109], (instregex "(V?)HADDPDrm", "(V?)HSUBPDrm", "(V?)HSUBPSrm")>; -def SBWriteResGroup110 : SchedWriteRes<[SBPort5]> { - let Latency = 12; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup110], (instregex "(V?)AESIMCrr")>; - def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { let Latency = 12; let NumMicroOps = 2; @@ -2009,16 +1992,6 @@ def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI16m", "SUB_FI16m", "SUB_FI32m")>; -def SBWriteResGroup115 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> { - let Latency = 13; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup115], (instregex "(V?)AESDECLASTrm", - "(V?)AESDECrm", - "(V?)AESENCLASTrm", - "(V?)AESENCrm")>; - def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> { let Latency = 14; let NumMicroOps = 1; @@ -2067,13 +2040,6 @@ def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23]> { def: InstRW<[SBWriteResGroup121], (instregex "(V?)PCMPISTRIrm", "(V?)PCMPISTRM128rm")>; -def SBWriteResGroup122 : SchedWriteRes<[SBPort5,SBPort23]> { - let Latency = 18; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup122], (instregex "(V?)AESIMCrm")>; - def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> { let Latency = 20; let NumMicroOps = 2; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 99859e57377..6826347ad77 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -212,29 +212,37 @@ def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort16, SKLPort5, SKLPort23]> { } // AES instructions. -def : WriteRes<WriteAESDecEnc, [SKLPort5]> { // Decryption, encryption. - let Latency = 7; +def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; let ResourceCycles = [1]; } -def : WriteRes<WriteAESDecEncLd, [SKLPort5, SKLPort23]> { - let Latency = 7; - let ResourceCycles = [1, 1]; +def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } -def : WriteRes<WriteAESIMC, [SKLPort5]> { // InvMixColumn. - let Latency = 14; + +def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; let ResourceCycles = [2]; } -def : WriteRes<WriteAESIMCLd, [SKLPort5, SKLPort23]> { +def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { let Latency = 14; - let ResourceCycles = [2, 1]; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5]> { // Key Generation. - let Latency = 10; - let ResourceCycles = [2, 8]; + +def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; } -def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23]> { - let Latency = 10; - let ResourceCycles = [2, 7, 1]; +def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; } // Carry-less multiplication instructions. @@ -1371,11 +1379,7 @@ def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKLWriteResGroup47], (instregex "AESDECLASTrr", - "AESDECrr", - "AESENCLASTrr", - "AESENCrr", - "MMX_PMADDUBSWrr", +def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr", "MMX_PMADDWDirr", "MMX_PMULHRSWrr", "MMX_PMULHUWirr", @@ -1389,10 +1393,6 @@ def: InstRW<[SKLWriteResGroup47], (instregex "AESDECLASTrr", "RCPSSr", "RSQRTPSr", "RSQRTSSr", - "VAESDECLASTrr", - "VAESDECrr", - "VAESENCLASTrr", - "VAESENCrr", "VRCPPSYr", "VRCPPSr", "VRCPSSr", @@ -2394,13 +2394,6 @@ def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort015 } def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; -def SKLWriteResGroup104 : SchedWriteRes<[SKLPort0]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SKLWriteResGroup104], (instregex "(V?)AESIMCrr")>; - def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> { let Latency = 8; let NumMicroOps = 2; @@ -2828,11 +2821,7 @@ def SKLWriteResGroup132 : SchedWriteRes<[SKLPort0,SKLPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup132], (instregex "(V?)AESDECLASTrm", - "(V?)AESDECrm", - "(V?)AESENCLASTrm", - "(V?)AESENCrm", - "(V?)RCPPSm", +def: InstRW<[SKLWriteResGroup132], (instregex "(V?)RCPPSm", "(V?)RSQRTPSm")>; def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { @@ -3232,13 +3221,6 @@ def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr", "VDIVPDrr", "VDIVSDrr")>; -def SKLWriteResGroup167 : SchedWriteRes<[SKLPort0,SKLPort23]> { - let Latency = 14; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SKLWriteResGroup167], (instregex "(V?)AESIMCrm")>; - def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> { let Latency = 14; let NumMicroOps = 3; @@ -3457,13 +3439,6 @@ def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { } def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>; -def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> { - let Latency = 20; - let NumMicroOps = 11; - let ResourceCycles = [3,6,2]; -} -def: InstRW<[SKLWriteResGroup194], (instregex "(V?)AESKEYGENASSIST128rr")>; - def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> { let Latency = 21; let NumMicroOps = 2; @@ -3558,13 +3533,6 @@ def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015, } def: InstRW<[SKLWriteResGroup203], (instregex "(V?)PCMPESTRM128rm")>; -def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> { - let Latency = 25; - let NumMicroOps = 11; - let ResourceCycles = [3,6,1,1]; -} -def: InstRW<[SKLWriteResGroup204], (instregex "(V?)AESKEYGENASSIST128rm")>; - def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> { let Latency = 26; let NumMicroOps = 2; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 9d5e5804241..7e0a82f761b 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -212,29 +212,37 @@ def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort16, SKXPort5, SKXPort23]> { } // AES instructions. -def : WriteRes<WriteAESDecEnc, [SKXPort5]> { // Decryption, encryption. - let Latency = 7; +def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; let ResourceCycles = [1]; } -def : WriteRes<WriteAESDecEncLd, [SKXPort5, SKXPort23]> { - let Latency = 7; - let ResourceCycles = [1, 1]; +def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } -def : WriteRes<WriteAESIMC, [SKXPort5]> { // InvMixColumn. - let Latency = 14; + +def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; let ResourceCycles = [2]; } -def : WriteRes<WriteAESIMCLd, [SKXPort5, SKXPort23]> { +def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> { let Latency = 14; - let ResourceCycles = [2, 1]; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : WriteRes<WriteAESKeyGen, [SKXPort0, SKXPort5]> { // Key Generation. - let Latency = 10; - let ResourceCycles = [2, 8]; + +def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; } -def : WriteRes<WriteAESKeyGenLd, [SKXPort0, SKXPort5, SKXPort23]> { - let Latency = 10; - let ResourceCycles = [2, 7, 1]; +def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; } // Carry-less multiplication instructions. @@ -2179,11 +2187,7 @@ def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup49], (instregex "AESDECLASTrr", - "AESDECrr", - "AESENCLASTrr", - "AESENCrr", - "MMX_PMADDUBSWrr", +def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMADDUBSWrr", "MMX_PMADDWDirr", "MMX_PMULHRSWrr", "MMX_PMULHUWirr", @@ -2197,10 +2201,6 @@ def: InstRW<[SKXWriteResGroup49], (instregex "AESDECLASTrr", "RCPSSr", "RSQRTPSr", "RSQRTSSr", - "VAESDECLASTrr", - "VAESDECrr", - "VAESENCLASTrr", - "VAESENCrr", "VRCP14PDZ128r(b?)(k?)(z?)", "VRCP14PDZ256r(b?)(k?)(z?)", "VRCP14PSZ128r(b?)(k?)(z?)", @@ -3852,13 +3852,6 @@ def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,S } def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>; -def SKXWriteResGroup115 : SchedWriteRes<[SKXPort0]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SKXWriteResGroup115], (instregex "(V?)AESIMCrr")>; - def SKXWriteResGroup116 : SchedWriteRes<[SKXPort015]> { let Latency = 8; let NumMicroOps = 2; @@ -4702,16 +4695,8 @@ def SKXWriteResGroup147 : SchedWriteRes<[SKXPort0,SKXPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup147], (instregex "AESDECLASTrm", - "AESDECrm", - "AESENCLASTrm", - "AESENCrm", - "RCPPSm", +def: InstRW<[SKXWriteResGroup147], (instregex "RCPPSm", "RSQRTPSm", - "VAESDECLASTrm", - "VAESDECrm", - "VAESENCLASTrm", - "VAESENCrm", "VRCP14PDZ128m(b?)(k?)(z?)", "VRCP14PSZ128m(b?)(k?)(z?)", "VRCP14SDrm(b?)(k?)(z?)", @@ -5509,13 +5494,6 @@ def: InstRW<[SKXWriteResGroup184], (instregex "DIVPDrr", "VDIVSDZrr(b?)(_Int)?(k?)(z?)", "VDIVSDrr")>; -def SKXWriteResGroup185 : SchedWriteRes<[SKXPort0,SKXPort23]> { - let Latency = 14; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SKXWriteResGroup185], (instregex "(V?)AESIMCrm")>; - def SKXWriteResGroup186 : SchedWriteRes<[SKXPort23,SKXPort015]> { let Latency = 14; let NumMicroOps = 3; @@ -5844,13 +5822,6 @@ def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { } def: InstRW<[SKXWriteResGroup220], (instregex "MWAITrr")>; -def SKXWriteResGroup221 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { - let Latency = 20; - let NumMicroOps = 11; - let ResourceCycles = [3,6,2]; -} -def: InstRW<[SKXWriteResGroup221], (instregex "(V?)AESKEYGENASSIST128rr")>; - def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23]> { let Latency = 21; let NumMicroOps = 2; @@ -6007,13 +5978,6 @@ def SKXWriteResGroup235 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015, } def: InstRW<[SKXWriteResGroup235], (instregex "(V?)PCMPESTRM128rm")>; -def SKXWriteResGroup236 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { - let Latency = 25; - let NumMicroOps = 11; - let ResourceCycles = [3,6,1,1]; -} -def: InstRW<[SKXWriteResGroup236], (instregex "(V?)AESKEYGENASSIST128rm")>; - def SKXWriteResGroup237 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { let Latency = 26; let NumMicroOps = 4; |
