diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 4 | 
3 files changed, 10 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index 309caee42b9..f45ebdc5350 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -1538,7 +1538,10 @@ bool ARMConstantIslands::UndoLRSpillRestore() {      if (MI->getOpcode() == ARM::tPOP_RET &&          MI->getOperand(2).getReg() == ARM::PC &&          MI->getNumExplicitOperands() == 3) { -      BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); +      // Create the new insn and copy the predicate from the old. +      BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)) +        .addOperand(MI->getOperand(0)) +        .addOperand(MI->getOperand(1));        MI->eraseFromParent();        MadeChange = true;      } diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 9a96dc7fdae..bba0ab6450c 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -385,13 +385,13 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {  }  let isReturn = 1, isTerminator = 1, isBarrier = 1 in { -  def tBX_RET : tPseudoExpand<(outs), (ins), Size2Bytes, IIC_Br, -                   [(ARMretflag)], (tBX LR, (ops 14, zero_reg))>; +  def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br, +                   [(ARMretflag)], (tBX LR, pred:$p)>;    // Alternative return instruction used by vararg functions. -  def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm), +  def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),                     Size2Bytes, IIC_Br, [], -                   (tBX GPR:$Rm, (ops 14, zero_reg))>; +                   (tBX GPR:$Rm, pred:$p)>;  }  // All calls clobber the non-callee saved registers. SP is marked as a use to diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp index 48211d852f8..c258870e48a 100644 --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -273,8 +273,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize); -    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) -      .addReg(ARM::R3, RegState::Kill); +    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) +      .addReg(ARM::R3, RegState::Kill));      // erase the old tBX_RET instruction      MBB.erase(MBBI);    }  | 

