diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.cpp | 19 |
2 files changed, 22 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 7a2f2570b34..0e2c98097ed 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -45,9 +45,11 @@ def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", "Enable 3DNow! Athlon instructions", [Feature3DNow]>; +// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied +// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) +// without disabling 64-bit mode. def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", - "Support 64-bit instructions", - [FeatureSSE2]>; + "Support 64-bit instructions">; def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", "Bit testing of memory is slow">; @@ -70,7 +72,7 @@ def : Proc<"pentium2", [FeatureMMX]>; def : Proc<"pentium3", [FeatureSSE1]>; def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; def : Proc<"pentium4", [FeatureSSE2]>; -def : Proc<"x86-64", [Feature64Bit, FeatureSlowBTMem]>; +def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; @@ -87,10 +89,14 @@ def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; -def : Proc<"k8", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; -def : Proc<"opteron", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; -def : Proc<"athlon64", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; -def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; +def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; +def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; +def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; +def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; def : Proc<"winchip-c6", [FeatureMMX]>; def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 185f45b4cf1..5ceafa4c593 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -327,21 +327,20 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit) } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); - if (Is64Bit && X86SSELevel < SSE2) { - // Make sure SSE2 is enabled, it is available on all X86-64 CPUs. - X86SSELevel = SSE2; - } - } - - // If requesting codegen for X86-64, make sure that 64-bit features - // are enabled. - if (Is64Bit) { + // If requesting codegen for X86-64, make sure that 64-bit features + // are enabled. + if (Is64Bit) HasX86_64 = true; + // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. + if (Is64Bit && X86SSELevel < SSE2) + X86SSELevel = SSE2; } - assert(!Is64Bit || HasX86_64); + DOUT << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"; + assert((!Is64Bit || HasX86_64) && + "64-bit code requested on a subtarget that doesn't support it!"); // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. |
