diff options
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 36 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 69 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td | 26 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 31 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 2 |
5 files changed, 139 insertions, 25 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 9fcf917a853..0714f8cb522 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -463,6 +463,8 @@ public: Match_RequiresSameSrcAndDst, Match_NoFCCRegisterForCurrentISA, Match_NonZeroOperandForSync, + Match_RequiresPosSizeRange0_32, + Match_RequiresPosSizeRange33_64, #define GET_OPERAND_DIAGNOSTIC_TYPES #include "MipsGenAsmMatcher.inc" #undef GET_OPERAND_DIAGNOSTIC_TYPES @@ -4977,6 +4979,28 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) return Match_RequiresDifferentOperands; return Match_Success; + case Mips::DINS: + case Mips::DINS_MM64R6: { + assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && + "Operands must be immediates for dins!"); + const signed Pos = Inst.getOperand(2).getImm(); + const signed Size = Inst.getOperand(3).getImm(); + if ((0 > (Pos + Size)) || ((Pos + Size) > 32)) + return Match_RequiresPosSizeRange0_32; + return Match_Success; + } + case Mips::DINSM: + case Mips::DINSM_MM64R6: + case Mips::DINSU: + case Mips::DINSU_MM64R6: { + assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && + "Operands must be immediates for dinsm/dinsu!"); + const signed Pos = Inst.getOperand(2).getImm(); + const signed Size = Inst.getOperand(3).getImm(); + if ((32 >= (Pos + Size)) || ((Pos + Size) > 64)) + return Match_RequiresPosSizeRange33_64; + return Match_Success; + } } uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags; @@ -5169,6 +5193,18 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_MemSImm16: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 16-bit signed offset"); + case Match_RequiresPosSizeRange0_32: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 0 .. 32", + SMRange(ErrorStart, ErrorEnd)); + } + case Match_RequiresPosSizeRange33_64: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 33 .. 64", + SMRange(ErrorStart, ErrorEnd)); + } } llvm_unreachable("Implement any new match types added!"); diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 41b965731e3..8bd2e791998 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -519,6 +519,10 @@ static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); +template <typename InsnType> +static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -1051,6 +1055,60 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, return MCDisassembler::Success; } +// Override the generated disassembler to produce DINS all the time. This is +// for feature / behaviour parity with binutils. +template <typename InsnType> +static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, + const void *Decoder) { + unsigned Msbd = fieldFromInstruction(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + bool IsMicroMips = false; + + switch (MI.getOpcode()) { + case Mips::DINS_MM64R6: + IsMicroMips = true; + LLVM_FALLTHROUGH; + case Mips::DINS: + Pos = Lsb; + Size = Msbd + 1 - Pos; + break; + case Mips::DINSM_MM64R6: + IsMicroMips = true; + LLVM_FALLTHROUGH; + case Mips::DINSM: + Pos = Lsb; + Size = Msbd + 33 - Pos; + break; + case Mips::DINSU_MM64R6: + IsMicroMips = true; + LLVM_FALLTHROUGH; + case Mips::DINSU: + Pos = Lsb + 32; + // mbsd = pos + size - 33 + // mbsd - pos + 33 = size + Size = Msbd + 33 - Pos; + break; + default: + llvm_unreachable("Unknown DINS instruction!"); + } + + // Although the format of the instruction is similar, rs and rt are swapped + // for microMIPS64R6. + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + if (IsMicroMips) + std::swap(Rs, Rt); + + MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); + MI.addOperand(MCOperand::createImm(Pos)); + MI.addOperand(MCOperand::createImm(Size)); + + return MCDisassembler::Success; +} /// Read two bytes from the ArrayRef and return 16 bit halfword sorted /// according to the given endianness. static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -2260,15 +2318,10 @@ static DecodeStatus DecodeInsSize(MCInst &Inst, uint64_t Address, const void *Decoder) { // First we need to grab the pos(lsb) from MCInst. + // This function only handles the 32 bit variants of ins, as dins + // variants are handled differently. int Pos = Inst.getOperand(2).getImm(); - if (Inst.getOpcode() == Mips::DINSU) - Pos += 32; - int Size; - if (Inst.getOpcode() == Mips::DINSM || - Inst.getOpcode() == Mips::DINSU) - Size = (int) Insn - Pos + 33; - else - Size = (int) Insn - Pos + 1; + int Size = (int) Insn - Pos + 1; Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td index a37b31643ac..4f7248e8d01 100644 --- a/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -168,8 +168,9 @@ class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, immZExt5Plus1, MipsIns>; class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64, immZExt5, immZExtRange2To64, MipsIns>; -class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1, - immZExt5, immZExt5Plus1, MipsIns>; +class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5_report_uimm6, + uimm5_inssize_plus1, immZExt5, immZExt5Plus1, + MipsIns>; class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>; class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd, @@ -382,12 +383,14 @@ let DecoderNamespace = "MicroMipsR6" in { ISA_MICROMIPS64R6; def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC, ISA_MICROMIPS64R6; - def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC, - ISA_MICROMIPS64R6; - def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC, - ISA_MICROMIPS64R6; - def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC, - ISA_MICROMIPS64R6; + let DecoderMethod = "DecodeDINS" in { + def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC, + ISA_MICROMIPS64R6; + } def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC, ISA_MICROMIPS64R6; def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC, @@ -562,3 +565,10 @@ def : MipsInstAlias<"dsrl $rd, $rt", def : MipsInstAlias<"dsll $rd, $rt", (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6; +def : MipsInstAlias<"dins $rt, $rs, $pos, $size", + (DINSM_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, + uimm_range_2_64:$size), 0>, ISA_MICROMIPS64R6; +def : MipsInstAlias<"dins $rt, $rs, $pos, $size", + (DINSU_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs, + uimm5_plus32:$pos, uimm5_plus1:$size), 0>, + ISA_MICROMIPS64R6; diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index a5c3096739c..3f0930355af 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -327,14 +327,23 @@ let AdditionalPredicates = [NotInMicroMips] in { def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>, ISA_MIPS64R2; - def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, immZExt5, - immZExt5Plus1, MipsIns>, EXT_FM<7>, ISA_MIPS64R2; - def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, - immZExt5Plus32, immZExt5Plus1, MipsIns>, - EXT_FM<6>, ISA_MIPS64R2; - def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64, - immZExt5, immZExtRange2To64, MipsIns>, - EXT_FM<5>, ISA_MIPS64R2; + // The 'pos + size' constraints for code generation are enforced by the + // code that lowers into MipsISD::Ins. + // For assembly parsing, we alias dinsu and dinsm to dins, and match by + // operand were possible then check the 'pos + size' in MipsAsmParser. + // We override the generated decoder to enforce that dins always comes out + // for dinsm and dinsu like binutils. + let DecoderMethod = "DecodeDINS" in { + def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, + immZExt5, immZExt5Plus1, MipsIns>, EXT_FM<7>, + ISA_MIPS64R2; + def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, + immZExt5Plus32, immZExt5Plus1, MipsIns>, + EXT_FM<6>, ISA_MIPS64R2; + def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64, + immZExt5, immZExtRange2To64, MipsIns>, + EXT_FM<5>, ISA_MIPS64R2; + } } let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in { @@ -825,6 +834,12 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dsll $rd, $rt", (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, ISA_MIPS3; + def : MipsInstAlias<"dins $rt, $rs, $pos, $size", + (DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, + uimm_range_2_64:$size), 0>, ISA_MIPS64R2; + def : MipsInstAlias<"dins $rt, $rs, $pos, $size", + (DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, + uimm5_plus1:$size), 0>, ISA_MIPS64R2; // Two operand (implicit 0 selector) versions: def : MipsInstAlias<"dmtc0 $rt, $rd", diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 22410864d70..0ff1c4cf145 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -883,7 +883,7 @@ def uimm16_altrelaxed : Operand<i32> { // Like uimm5 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_report_uimm6 : Operand<i32> { - let PrintMethod = "printUImm<5>"; + let PrintMethod = "printUImm<6>"; let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; } |