diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPU.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUCallingConv.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUSubtarget.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/Processors.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 2 |
6 files changed, 24 insertions, 9 deletions
diff --git a/llvm/lib/Target/R600/AMDGPU.td b/llvm/lib/Target/R600/AMDGPU.td index a722f555b85..f63617f8772 100644 --- a/llvm/lib/Target/R600/AMDGPU.td +++ b/llvm/lib/Target/R600/AMDGPU.td @@ -87,6 +87,8 @@ def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", [Feature64BitPtr, FeatureFP64]>; +def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", + [Feature64BitPtr, FeatureFP64]>; //===----------------------------------------------------------------------===// def AMDGPUInstrInfo : InstrInfo { diff --git a/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp index 5522a6b82d5..30577909e80 100644 --- a/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -167,6 +167,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) { } void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { + const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); unsigned MaxSGPR = 0; unsigned MaxVGPR = 0; bool VCCUsed = false; @@ -267,13 +268,24 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) { OutStreamer.EmitIntValue(RsrcReg, 4); OutStreamer.EmitIntValue(S_00B028_VGPRS(MaxVGPR / 4) | S_00B028_SGPRS(MaxSGPR / 8), 4); + unsigned LDSAlignShift; + if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) { + // LDS is allocated in 64 dword blocks + LDSAlignShift = 8; + } else { + // LDS is allocated in 128 dword blocks + LDSAlignShift = 9; + } + unsigned LDSBlocks = + RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift; + if (MFI->ShaderType == ShaderType::COMPUTE) { OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4); - OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(RoundUpToAlignment(MFI->LDSSize, 256) >> 8), 4); + OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4); } if (MFI->ShaderType == ShaderType::PIXEL) { OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4); - OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(RoundUpToAlignment(MFI->LDSSize, 256) >> 8), 4); + OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4); OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4); OutStreamer.EmitIntValue(MFI->PSInputAddr, 4); } diff --git a/llvm/lib/Target/R600/AMDGPUCallingConv.td b/llvm/lib/Target/R600/AMDGPUCallingConv.td index 3535e35f4fb..fbcdc6aec4f 100644 --- a/llvm/lib/Target/R600/AMDGPUCallingConv.td +++ b/llvm/lib/Target/R600/AMDGPUCallingConv.td @@ -48,7 +48,7 @@ def CC_AMDGPU_Kernel : CallingConv<[ ]>; def CC_AMDGPU : CallingConv<[ - CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() == " + CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() >= " "AMDGPUSubtarget::SOUTHERN_ISLANDS && " "State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"# "ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>, @@ -57,5 +57,5 @@ def CC_AMDGPU : CallingConv<[ "State.getMachineFunction().getInfo<R600MachineFunctionInfo>()->" "ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>, CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>()"# - ".getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo<CC_SI>> + ".getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo<CC_SI>> ]>; diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.h b/llvm/lib/Target/R600/AMDGPUSubtarget.h index c5345cc764c..c08cd6a6b85 100644 --- a/llvm/lib/Target/R600/AMDGPUSubtarget.h +++ b/llvm/lib/Target/R600/AMDGPUSubtarget.h @@ -33,7 +33,8 @@ public: R700, EVERGREEN, NORTHERN_ISLANDS, - SOUTHERN_ISLANDS + SOUTHERN_ISLANDS, + SEA_ISLANDS }; private: diff --git a/llvm/lib/Target/R600/Processors.td b/llvm/lib/Target/R600/Processors.td index 4631c04c41e..31079d3eff9 100644 --- a/llvm/lib/Target/R600/Processors.td +++ b/llvm/lib/Target/R600/Processors.td @@ -48,6 +48,6 @@ def : Proc<"pitcairn", SI_Itin, [FeatureSouthernIslands]>; def : Proc<"verde", SI_Itin, [FeatureSouthernIslands]>; def : Proc<"oland", SI_Itin, [FeatureSouthernIslands]>; def : Proc<"hainan", SI_Itin, [FeatureSouthernIslands]>; -def : Proc<"bonaire", SI_Itin, [FeatureSouthernIslands]>; -def : Proc<"kabini", SI_Itin, [FeatureSouthernIslands]>; -def : Proc<"kaveri", SI_Itin, [FeatureSouthernIslands]>; +def : Proc<"bonaire", SI_Itin, [FeatureSeaIslands]>; +def : Proc<"kabini", SI_Itin, [FeatureSeaIslands]>; +def : Proc<"kaveri", SI_Itin, [FeatureSeaIslands]>; diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 92a53ddeb9f..048c1579b66 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -23,7 +23,7 @@ def InterpSlot : Operand<i32> { } def isSI : Predicate<"Subtarget.getGeneration() " - "== AMDGPUSubtarget::SOUTHERN_ISLANDS">; + ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; def WAIT_FLAG : InstFlag<"printWaitFlag">; |
